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This driver is based on the one for NPCM7xx, because the WPCM450 is a
predecessor of those SoCs. Notable differences:
- On WPCM450, the GPIO registers are not organized in multiple banks,
but rather placed continually into the same register block. This
affects how register offsets are computed.
- Pinmux nodes can explicitly select GPIO mode, whereas in the npcm7xx
driver, this happens automatically when a GPIO is requested.
Some functionality implemented in the hardware was (for now) left unused
in the driver, specifically blinking and pull-up/down.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20220129115228.2257310-6-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This driver can have up to two regmaps. If the second one is registered
its debugfs entry will have the same name as the first one and the
following error will be printed:
[ 2.242568] debugfs: Directory 'e2004064.pinctrl' with parent 'regmap' already present!
Give the second regmap a name to avoid this.
Fixes: 076d9e71bcf8 ("pinctrl: ocelot: convert pinctrl to regmap")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Colin Foster <colin.foster@in-advantage.com>
Link: https://lore.kernel.org/r/20220216122727.1005041-1-michael@walle.cc
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Prior to commit ad96111e658a ("pinctrl: ocelot: combine get resource and
ioremap into single call") the resource index was 1, now it is 0. But 0
is the base region for the pinctrl block. Fix it.
I noticed this because there was an error that the memory region was
ioremapped twice.
Fixes: ad96111e658a ("pinctrl: ocelot: combine get resource and ioremap into single call")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Colin Foster <colin.foster@in-advantage.com>
Link: https://lore.kernel.org/r/20220216082020.981797-1-michael@walle.cc
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add i.MX93 pinctrl driver
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220228010103.2725893-2-peng.fan@oss.nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Change "mediatek,rsel_resistance_in_si_unit" to "mediatek,rsel-resistance-in-si-unit"
Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Link: https://lore.kernel.org/r/20220216032124.28067-4-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This commit includes pinctrl driver for mt8186.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Link: https://lore.kernel.org/r/20220216032124.28067-3-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Conflicts:
drivers/pinctrl/pinctrl-starfive.c
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.18-1
* Introduce support for Alder Lake-N (required to revert misplaced ID)
* Add support for Raptor Lake-S
* Add support for Ice Lake-N (MacBookPro16,2)
* Miscellaneous fixes
The following is an automated git shortlog grouped by driver:
alderlake:
- Add Intel Alder Lake-N pin controller support
- Add Raptor Lake-S ACPI ID
baytrail:
- Clear direct_irq_en flag on broken configs
icelake:
- Add Ice Lake-N PCH pin controller support
intel:
- Fix a glitch when updating IRQ flags on a preconfigured line
- fix unexpected interrupt
Place correctly CONFIG_PINCTRL_ST in the Makefile:
- Place correctly CONFIG_PINCTRL_ST in the Makefile
tigerlake:
- Revert "Add Alder Lake-M ACPI ID"
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This driver, like several others, uses a chained IRQ for each GPIO bank,
and forwards .irq_set_wake to the GPIO bank's upstream IRQ. As a result,
a call to irq_set_irq_wake() needs to lock both the upstream and
downstream irq_desc's. Lockdep considers this to be a possible deadlock
when the irq_desc's share lockdep classes, which they do by default:
============================================
WARNING: possible recursive locking detected
5.17.0-rc3-00394-gc849047c2473 #1 Not tainted
--------------------------------------------
init/307 is trying to acquire lock:
c2dfe27c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0
but task is already holding lock:
c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&irq_desc_lock_class);
lock(&irq_desc_lock_class);
*** DEADLOCK ***
May be due to missing lock nesting notation
4 locks held by init/307:
#0: c1f29f18 (system_transition_mutex){+.+.}-{3:3}, at: __do_sys_reboot+0x90/0x23c
#1: c20f7760 (&dev->mutex){....}-{3:3}, at: device_shutdown+0xf4/0x224
#2: c2e804d8 (&dev->mutex){....}-{3:3}, at: device_shutdown+0x104/0x224
#3: c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0
stack backtrace:
CPU: 0 PID: 307 Comm: init Not tainted 5.17.0-rc3-00394-gc849047c2473 #1
Hardware name: Allwinner sun8i Family
unwind_backtrace from show_stack+0x10/0x14
show_stack from dump_stack_lvl+0x68/0x90
dump_stack_lvl from __lock_acquire+0x1680/0x31a0
__lock_acquire from lock_acquire+0x148/0x3dc
lock_acquire from _raw_spin_lock_irqsave+0x50/0x6c
_raw_spin_lock_irqsave from __irq_get_desc_lock+0x58/0xa0
__irq_get_desc_lock from irq_set_irq_wake+0x2c/0x19c
irq_set_irq_wake from irq_set_irq_wake+0x13c/0x19c
[tail call from sunxi_pinctrl_irq_set_wake]
irq_set_irq_wake from gpio_keys_suspend+0x80/0x1a4
gpio_keys_suspend from gpio_keys_shutdown+0x10/0x2c
gpio_keys_shutdown from device_shutdown+0x180/0x224
device_shutdown from __do_sys_reboot+0x134/0x23c
__do_sys_reboot from ret_fast_syscall+0x0/0x1c
However, this can never deadlock because the upstream and downstream
IRQs are never the same (nor do they even involve the same irqchip).
Silence this erroneous lockdep splat by applying what appears to be the
usual fix of moving the GPIO IRQs to separate lockdep classes.
Fixes: a59c99d9eaf9 ("pinctrl: sunxi: Forward calls to irq_set_irq_wake")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220216040037.22730-1-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The commit that sets the direction directly without calling
pinctrl_gpio_direction(), forgot to add chip->base to the offset when
calling sunxi_pmx_gpio_set_direction().
This caused failures for various Allwinner boards which have two
GPIO blocks.
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Reported-by: 5kft <5kft@5kft.org>
Suggested-by: 5kft <5kft@5kft.org>
Reported-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Fixes: 8df89a7cbc63 (pinctrl-sunxi: don't call pinctrl_gpio_direction())
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Tested-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/0f536cd8-01db-5d16-2cec-ec6d19409a49@xs4all.nl
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
[Picked from linux-next to pinctrl fixes]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.18 (take two)
- Share more pin group data, to reduce kernel size and ease review,
- Improve the pin control table validator,
- Add support for the new R-Car S4-8 SoC,
- Miscellaneous fixes and improvements.
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git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung pinctrl DTS and driver changes for v5.18
Conversion of Samsung pinctrl bindings to dtschema followed up with
alignment of DTS files to the dtschema.
The entire work consists of three parts but everything should be merged
at once to avoid dtschema check errors:
1. Samsung pinctrl driver change necessary to accept new DTS (driver
depends on node names and this has to be adjusted because of dtschema).
2. Conversion to dtschema which brings requirement of different naming
of the GPIO nodes.
3. DTS commits depending on driver (1) above, which convert all GPIO pin
bank names to new naming, required by dtschema.
This also includes few cleanups around DTS which are here to avoid
any merge conflicts.
The Samsung pinctrl driver changes are backwards compatible. However
the DTS changes (renaming nodes) could cause problems in out-of-tree or
other project implementations of the driver.
* tag 'samsung-dt-pinctrl-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (28 commits)
arm64: dts: exynos: use dedicated wake-up pinctrl compatible in ExynosAutov9
ARM: dts: s5pv210: align pinctrl with dtschema
ARM: dts: s3c64xx: align pinctrl with dtschema
ARM: dts: s3c24xx: align pinctrl with dtschema
arm64: dts: exynos: align pinctrl with dtschema in ExynosAutov9
arm64: dts: exynos: align pinctrl with dtschema in Exynos7
arm64: dts: exynos: align pinctrl with dtschema in Exynos5433
ARM: dts: exynos: align pinctrl with dtschema in Exynos542x/5800
ARM: dts: exynos: align pinctrl with dtschema in Exynos5410
ARM: dts: exynos: align pinctrl with dtschema in Exynos5260
ARM: dts: exynos: align pinctrl with dtschema in Exynos5250
ARM: dts: exynos: align pinctrl with dtschema in Exynos4412
ARM: dts: exynos: align pinctrl with dtschema in Exynos4210
ARM: dts: exynos: align pinctrl with dtschema in Exynos3250
ARM: dts: s3c64xx: drop unneeded pinctrl wake-up interrupt mapping
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pi
ARM: dts: exynos: override pins by label in Peach Pi
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pit
ARM: dts: exynos: override pins by label in Peach Pit
ARM: dts: exynos: simplify PMIC DVS pin configuration in Odroid XU
...
Link: https://lore.kernel.org/r/20220129115352.13274-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add pins, groups, and functions for the Ethernet Time-Sensitive
Networking (TSN) interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/e0a1dc7d2435d28811e3acb361dae050eb3aabc9.1645457792.git.geert+renesas@glider.be
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Add pins, groups, and functions for the Quad SPI Controllers on the
Renesas R-Car S4-8 (R8A779F0) SoC.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/cd7f7feeabebf268adc9e050e348230e93b40829.1645457792.git.geert+renesas@glider.be
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Add pins, groups, and function for the PCIe Controllers on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/b2f95db490d13e8cb7d97a63d58d47933317e28a.1645457792.git.geert+renesas@glider.be
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Add pins, groups, and function for the Clock-Synchronized Serial
Interfaces with FIFO (MSIOF) on the Renesas R-Car S4-8 (R8A779F0) SoC.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/c625769714b1027a756dd2ed4a017eb24708a041.1645457792.git.geert+renesas@glider.be
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Add pins, groups, and function for the MMC interface on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/81a35c1fac4616d25501942848eb9662d477f9ef.1645457792.git.geert+renesas@glider.be
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Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the Renesas R-Car S4-8 (R8A779F0) SoC.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/dc6e25da42ac4bd19ca31b5b32b43a10a0e1aa7e.1645457792.git.geert+renesas@glider.be
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Add pins, groups, and functions for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) on the Renesas R-Car S4-8 (R8A779F0) SoC.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/2b85b8857c1189fa6ee33e2f57fe746d740481d1.1645457792.git.geert+renesas@glider.be
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Add pins, groups, and functions for the I2C Bus Interfaces (I2C) on the
Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/217f5b3e3888b5899c375d3cb1ec8780f6a9e19b.1645457792.git.geert+renesas@glider.be
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Add pins, groups, and functions for the Serial Communication Interfaces
with FIFO (SCIF) on the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/6369359a53483291ee536787c8a232462ff1b3a9.1645457792.git.geert+renesas@glider.be
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Add initial Pin Function Controller (PFC) support for the Renesas R-Car
S4-8 (R8A779F0) SoC, including bias, drive strength and voltage control.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/fd8201da404b7b0897130b254380ffc97f437266.1645457792.git.geert+renesas@glider.be
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Add PORT_GP_CFG_19() and PORT_GP_19() helper macros, to be used by the
r8a779f0 subdriver.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/f7fc711d065f78911bac1b616880ba3dbc858158.1645457792.git.geert+renesas@glider.be
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On the Lenovo Yoga Tablet 2 830 / 1050 / 1051 models the 32KHz PMU clk,
which can be muxed externally to SUS pin 5 and/or 6 is used as a clock
for the audio codec.
On the 830 and 1050 models, with ship with Android as factory OS the
pin-muxing for this is not setup by the BIOS.
Add a pinconf group + function for the pmu_clk on SUS pin 5 and 6 to
allow setting the pinmux up from within the x86-android-tablets
platform code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220223133153.730337-2-hdegoede@redhat.com
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Linus reports that some Renesas pin control sub-drivers are still
including <linux/gpio.h> instead of <linux/gpio/driver.h>. As these
sub-drivers don't need either, the includes can just be removed.
Reported-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/578825d779b45af745cc7623c7f69d2ddeadac4b.1645605227.git.geert+renesas@glider.be
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The checker failed to validate all enum IDs in the description of a
register with fixed-width register fields, due to a miscalculation of
the number of described states: each register field of n bits can have
"1 << n" possible states, not "1".
Increase SH_PFC_MAX_ENUMS accordingly, now more enum IDs are checked
(SH-Mobile AG5 has more than 4000 enum IDs defined).
Fixes: 12d057bad683b1c6 ("pinctrl: sh-pfc: checker: Add check for enum ID conflicts")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/6d8a6a05564f38f9d20464c1c17f96e52740cf6a.1645460429.git.geert+renesas@glider.be
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This adds pinctrl/GPIO support for Intel Ice Lake-N PCH. The Ice Lake-N
PCH GPIO is based on the same version of the Intel GPIO hardware than
Intel Cannon Lake with different set of pins and ACPI ID.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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This change driver adds pinctrl/GPIO support for Intel Alder Lake-N SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Intel Raptor Lake-S PCH has the same GPIO hardware than Alder Lake-S PCH
but the ACPI ID is different. Add this new ACPI ID to the list of supported
devices.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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It appears that last minute change moved ACPI ID of Alder Lake-M
to the INTC1055, which is already in the driver.
This ID on the other hand will be used elsewhere.
This reverts commit 258435a1c8187f559549e515d2f77fa0b57bcd27.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Check that there is only a single entry for each pin with drive strength
capabilities.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/382206e737710afd3059abe75bc41e324823e657.1640270559.git.geert+renesas@glider.be
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Check that there is only a single entry for each pin with pull-up and/or
pull-down capabilities.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/dbda76f342258f8029f0420fbe3f341a9abd6f01.1640270559.git.geert+renesas@glider.be
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Validate consistency of the pin control tables for pins with I/O voltage
capabilities. If a pin has I/O voltage register bits declarations
through .pin_to_pocctrl(), the SH_PFC_PIN_CFG_IO_VOLTAGE flag should be
set in the pin's configs, and vice versa.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/de81cced01ae3f26d341177d66d4b8e918fbfb76.1640270559.git.geert+renesas@glider.be
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Validate consistency of the pin control tables for pins with drive
strength capabilities. If a pin has drive strength register bits
declarations in drive_regs[], the SH_PFC_PIN_CFG_DRIVE_STRENGTH flag
should be set in the pin's configs, and vice versa.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0d5de01b5fe2c5fd23c3bea41077dc57ad105b9e.1640270559.git.geert+renesas@glider.be
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Validate consistency of the pin control tables for pins with pull-up
and/or pull-down capabilities. If a pin has bias register bits
declarations in bias_regs[] or through .pin_to_portcr(), the
corresponding SH_PFC_PIN_CFG_PULL* flags should be set in the pin's
configs, and vice versa, and the .get_bias() and .set_bias() callbacks
should be implemented.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/19b3e0773fbb36c015a43db683f79e75b0fec3ee.1640270559.git.geert+renesas@glider.be
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Add checks for discovering pin groups that could share pin data, as
sharing reduces kernel size.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e16fdf729156e13b591d2f082f2cc934da580074.1640270559.git.geert+renesas@glider.be
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Simplify the helper that checks if two strings are valid and identical.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/509c70041bcf4302e284758abe1fd8165644b505.1640270559.git.geert+renesas@glider.be
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Currently rcar_pin_to_bias_reg() takes a struct sh_pfc pointer, which is
only available after the pin control driver has been initialized,
thus preventing the checker from calling this function for validating
consistency of the pin control tables.
Fix this by replacing the parameter by a struct sh_pfc_soc_info pointer.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3065a12dde606bacec9e5f14f10cabeaae75e265.1640270559.git.geert+renesas@glider.be
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All implementations of the .pin_to_portcr() method implement the same
conversion from Port Control Register offset to virtual address. Factor
it out into the two callers.
Remove the pfc parameter, as it is no longer used.
Note that the failure handling in r8a7740_pin_to_portcr() is pro forma,
as the function is never called with an invalid pin number.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a485d4986a17259256988eb14e3a4c2b8d61c303.1640270559.git.geert+renesas@glider.be
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The pfc parameter of the .pin_to_pocctrl() method was never used.
It is a relic of the old I/O voltage handling before commit
8775306dcf48092f ("pinctrl: sh-pfc: refactor voltage setting").
Remove the parameter, as it prevents the checker from calling this
function for validating consistency of the pin control tables.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/822133086f32618c7fc920123c6a96f5d4ea7ad6.1640270559.git.geert+renesas@glider.be
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Pin group vin4_g8 is a subset of vin4_data24_a.
Pin group vin5_high8 is a subset of vin5_data16_a.
This reduces kernel size by 128 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cfb71c90c19723ba2770f7512f138e4b17857141.1640269757.git.geert+renesas@glider.be
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Pin group vin4_g8 is a subset of vin4_data24_a.
Pin group vin5_high8 is a subset of vin5_data16.
This reduces kernel size by 128 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/fd8779f5c7a397e8e4dc3604fe2af55e250a9f40.1640269757.git.geert+renesas@glider.be
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Pin group vin4_g8 is a subset of vin4_data24_a.
Pin group vin5_high8 is a subset of vin5_data16.
This reduces kernel size by 128 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1fc04bb08e2c26109509bd53b19ffbf9ce83d2f1.1640269757.git.geert+renesas@glider.be
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Pin group vin4_g8 is a subset of vin4_data24_a.
Pin group vin5_high8 is a subset of vin5_data16.
This reduces kernel size by 128 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/100605798d02cbd8695aedfaaaa8a3b63e3a281f.1640269757.git.geert+renesas@glider.be
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Pin group vin2_g8 is a subset of vin2_data24.
This reduces kernel size by 64 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a4f6a70344654456abea1f15539219d1e02a74fe.1640269757.git.geert+renesas@glider.be
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Pin group usb0_ovc_vbus is a subset of usb0.
Pin group usb1_pwen is a subset of usb1.
This reduces kernel size by 16 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/b9f37cf00064293b4b6f9068bda8c1ab819090f5.1640269757.git.geert+renesas@glider.be
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Pin groups sdi0_data[14] are subsets of sdi0_data8.
Pin groups sdi[12]_data1 are subsets of sdi[12]_data4.
This reduces kernel size by 56 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0f35f01666748217b93c2debc0098f9442061a1a.1640269757.git.geert+renesas@glider.be
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Pin groups sdhi[012]_data1 are subsets of sdhi[012]_data4.
This reduces kernel size by 24 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/96a5be0c34c66b302e16e915a7cc6272783aa73c.1640269757.git.geert+renesas@glider.be
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Pin groups sdhi[01]_data1 are subsets of sdhi[01]_data4.
Pin groups sdhi3_data[14] are subsets of sdhi3_data8.
This reduces kernel size by 56 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2f702b6c6114458a43a77ae04089e7f9e20482e5.1640269757.git.geert+renesas@glider.be
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Pin groups sdhi[01]_data1 are subsets of sdhi[01]_data4.
Pin groups sdhi[23]_data[14] are subsets of sdhi[23]_data8.
This reduces kernel size by 96 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/b638b7ad4a874e64a35057fa1ce6ab23db3406cf.1640269757.git.geert+renesas@glider.be
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