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path: root/drivers/pinctrl
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2022-04-23pinctrl: qcom: Update clock voting as optionalSrinivasa Rao Mandadapu
Update bulk clock voting to optional voting as ADSP bypass platform doesn't need macro and decodec clocks, as these macro and dcodec GDSC switches are maintained as power domains and operated from lpass clock drivers. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-8-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: qcom: Add SC7280 lpass pin configurationSrinivasa Rao Mandadapu
Add pin control support for SC7280 LPASS LPI. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-7-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: qcom: Extract chip specific LPASS LPI codeSrinivasa Rao Mandadapu
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver to allow reusing the common code in the addition of subsequent platforms. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-6-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: qcom: Update lpi pin group custiom functions with framework generic ↵Srinivasa Rao Mandadapu
functions Update custom pin group structure members with framework generic group_desc structure and replace the driver's custom pinctrl_ops with framework provided generic pin control group functions to avoid redundant code written in lpass lpi driver. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-5-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: qcom: Update macro name to LPI specificSrinivasa Rao Mandadapu
Update NO_SLEW macro to LPI_NO_SLEW macro as this driver lpi specific. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1650285427-19752-4-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-23pinctrl: nomadik: Add new MC2 configLinus Walleij
The MC2 MMC interface can be configured with the FBCLK (feedback clock) unconnected, leaving the pin available for reuse for something else. Add a group mc2_a_2 for this. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220418164317.864418-1-linus.walleij@linaro.org
2022-04-23pinctrl: thunderbay: Use devm_platform_ioremap_resource()Lv Ruyi
Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately.Make the code simpler without functional changes. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Lv Ruyi <lv.ruyi@zte.com.cn> Link: https://lore.kernel.org/r/20220418020238.2556989-1-lv.ruyi@zte.com.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl: rockchip: sort the rk3308_mux_recalced_data entriesLuca Ceresoli
All the entries are sorted according to num/pin except for two entries. Sort them too. Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220420142432.248565-2-luca.ceresoli@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl: rockchip: fix RK3308 pinmux bitsLuca Ceresoli
Some of the pinmuxing bits described in rk3308_mux_recalced_data are wrong, pointing to non-existing registers. Fix the entire table. Also add a comment in front of each entry with the same string that appears in the datasheet to make the table easier to compare with the docs. This fix has been tested on real hardware for the gpio3b3_sel entry. Fixes: 7825aeb7b208 ("pinctrl: rockchip: add rk3308 SoC support") Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220420142432.248565-1-luca.ceresoli@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22Merge tag 'samsung-pinctrl-fixes-5.18' of ↵Linus Walleij
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into fixes Samsung pinctrl drivers fixes for v5.18 1. Fix sparse warning introduced in v5.18-rc1. 2. Fix possible unmet Kconfig dependency with COMPILE_TEST, present since v4.3 or earlier.
2022-04-22pinctrl: ingenic: Garbage-collect code paths for SoCs disabled by configPaul Cercueil
By being a bit smarter about how the SoC version checks are performed, it is possible to have all the code paths that correspond to SoCs disabled in the kernel config automatically marked as dead code by the compiler, and therefore garbage-collected. With this patch, when compiling a kernel that only targets the JZ4760 for instance, the driver is now about 4.5 KiB smaller. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220412162218.32509-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl: max77620: drop unneeded MODULE_ALIASKrzysztof Kozlowski
The MODULE_DEVICE_TABLE already creates proper alias for platform driver. Having another MODULE_ALIAS causes the alias to be duplicated. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407202509.23228-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl: meson: fix unused variable warningQianggui Song
The kernel test robot reported a warning as below: >> drivers/pinctrl/meson/pinctrl-meson-s4.c:178:27: warning: unused variable 'tdm_sclk1_c_pins' [-Wunused-const-variable] static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 }; Fix it by adding missing description about this pins Fixes: 775214d389c2 ("pinctrl: meson: add pinctrl driver support for Meson-S4 Soc") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220330023720.18238-1-qianggui.song@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl: mediatek: mt8195: enable driver on mtk platformsFabien Parent
Set the pinctrl driver as built-in by default if ARM64 and ARCH_MEDIATEK are enabled. Fixes: 6cf5e9ef362a ("pinctrl: add pinctrl driver on mt8195") Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220327160813.2978637-1-fparent@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl/rockchip: support setting input-enable paramCaleb Connolly
Handle the PIN_CONFIG_INPUT_ENABLE param for configuring GPIOs as input. Signed-off-by: Caleb Connolly <kc@postmarketos.org> Link: https://lore.kernel.org/r/20220328005005.72492-3-kc@postmarketos.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-22pinctrl/rockchip: support deferring other gpio paramsCaleb Connolly
Add support for deferring other params like PIN_CONFIG_INPUT_ENABLE. This will be used to add support for PIN_CONFIG_INPUT_ENABLE to the driver. Fixes: e7165b1dff06 ("pinctrl/rockchip: add a queue for deferred pin output settings on probe") Fixes: 59dd178e1d7c ("gpio/rockchip: fetch deferred output settings on probe") Signed-off-by: Caleb Connolly <kc@postmarketos.org> Link: https://lore.kernel.org/r/20220328005005.72492-2-kc@postmarketos.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: stm32: Do not call stm32_gpio_get() for edge triggered IRQs in EOIMarek Vasut
The stm32_gpio_get() should only be called for LEVEL triggered interrupts, skip calling it for EDGE triggered interrupts altogether to avoid wasting CPU cycles in EOI handler. On this platform, EDGE triggered interrupts are the majority and LEVEL triggered interrupts are the exception no less, and the CPU cycles are not abundant. Fixes: 47beed513a85b ("pinctrl: stm32: Add level interrupt support to gpio irq chip") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Fabien Dessenne <fabien.dessenne@foss.st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Marc Zyngier <maz@kernel.org> Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-arm-kernel@lists.infradead.org To: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20220415215410.498349-1-marex@denx.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: Fix an error in pin-function table of SP7021Wells Lu
The first valid item of pin-function table should start from the third item. The first two items, due to historical and compatible reasons, should be dummy items. The two dummy items were removed accidentally in initial submission. This fix adds them back. Signed-off-by: Wells Lu <wellslutw@gmail.com> Link: https://lore.kernel.org/r/1650015688-19774-1-git-send-email-wellslutw@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: ocelot: add clock monitor option for LAN966xMichael Walle
The SoC supports a debug clock output of its internal clocks. Depending on the clk_sel input (GPIO_31) clk_mon (GPIO_30) will output either cpu_clk/64 or sys_clk/64. This is very useful for debugging and is missing in the pinmux table. Add it. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220326192848.2944519-2-michael@walle.cc Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: ocelot: add pwm output option for LAN966xMichael Walle
According to the reference manual, you can mux the PWM output on GPIO27 and GPIO51. This was missing in the pinmux table. Add it. Tested on a LAN9668 on GPIO51. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220326192848.2944519-1-michael@walle.cc Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: qcom-pmic-gpio: Add support for pmx65Rohit Agarwal
PMX65 pmic support gpio controller so add compatible. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1649048650-14059-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: bcm2835: implement hook for missing gpio-rangesStefan Wahren
The commit c8013355ead6 ("ARM: dts: gpio-ranges property is now required") fixed the GPIO probing issues caused by "pinctrl: bcm2835: Change init order for gpio hogs". This changed only the kernel DTS files. Unfortunately it isn't guaranteed that these files are shipped to all users. So implement the necessary backward compatibility for BCM2835 and BCM2711 platform. Fixes: 266423e60ea1 ("pinctrl: bcm2835: Change init order for gpio hogs") Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220409095129.45786-3-stefan.wahren@i2se.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-21pinctrl: samsung: fix missing GPIOLIB on ARM64 Exynos configKrzysztof Kozlowski
The Samsung pinctrl drivers depend on OF_GPIO, which is part of GPIOLIB. ARMv7 Exynos platform selects GPIOLIB and Samsung pinctrl drivers. ARMv8 Exynos selects only the latter leading to possible wrong configuration on ARMv8 build: WARNING: unmet direct dependencies detected for PINCTRL_EXYNOS Depends on [n]: PINCTRL [=y] && OF_GPIO [=n] && (ARCH_EXYNOS [=y] || ARCH_S5PV210 || COMPILE_TEST [=y]) Selected by [y]: - ARCH_EXYNOS [=y] Always select the GPIOLIB from the Samsung pinctrl drivers to fix the issue. This requires removing of OF_GPIO dependency (to avoid recursive dependency), so add dependency on OF for COMPILE_TEST cases. Reported-by: Necip Fazil Yildiran <fazilyildiran@gmail.com> Fixes: eed6b3eb20b9 ("arm64: Split out platform options to separate Kconfig") Cc: <stable@vger.kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20220420141407.470955-1-krzysztof.kozlowski@linaro.org
2022-04-21pinctrl: mediatek: moore: Fix build errorYueHaibing
If EINT_MTK is m and PINCTRL_MTK_V2 is y, build fails: drivers/pinctrl/mediatek/pinctrl-moore.o: In function `mtk_gpio_set_config': pinctrl-moore.c:(.text+0xa6c): undefined reference to `mtk_eint_set_debounce' drivers/pinctrl/mediatek/pinctrl-moore.o: In function `mtk_gpio_to_irq': pinctrl-moore.c:(.text+0xacc): undefined reference to `mtk_eint_find_irq' Select EINT_MTK for PINCTRL_MTK_V2 to fix this. Fixes: 8174a8512e3e ("pinctrl: mediatek: make MediaTek pinctrl v2 driver ready for buidling loadable module") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20220409105958.37412-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-20pinctrl: renesas: rzg2l: Restore pin config orderGeert Uytterhoeven
The PIN_CFG_* capabilities are always listed in the order they are defined, except in the "TMS/SWDIO" pin definition. Fix the order, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f9b18be9e5402531d058bd2479b4881377f9b8b6.1649857772.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: Remove unneeded #include <linux/init.h>Geert Uytterhoeven
The last __init annotations were removed from these source files almost one decade ago. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/fb71c409ea3ad76163496e305dc955ca8e84416d.1649681741.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabledLad Prabhakar
GPIO (PINCTRL) block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so instead of selecting PINCTRL_RZG2L config for each SoC select PINCTRL_RZG2L config option if ARCH_RZG2L is enabled. The ARCH_RZG2L config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220406075318.14385-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: rzg2l: Add RZ/G2UL supportBiju Das
RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible to take care of these differences by adding r9a07g043_data with r9a07g043_gpio_configs and rzg2l_dedicated_pins.common. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220401180230.19950-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: r8a77995: Add QSPI and RPC pins, groups, and functionsGeert Uytterhoeven
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77995 PFC driver. They are to be used when a QSPI Flash, Octal-SPI Flash, or HyperFlash is connected. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/19a3bccd0ec830846578a38b4c80dccb195109a0.1648547080.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: r8a77990: Add RPC pins, groups, and functionsGeert Uytterhoeven
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77990 PFC driver. They are to be used when an Octal-SPI Flash or HyperFlash is connected. Redefine the QSPI[01] pin groups using the RPC DQ[0:7] pin data, to save memory. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ec9735bb3468225e04ac6cb95e11a0e237b2b9ed.1648547080.git.geert+renesas@glider.be
2022-04-20pinctrl: renesas: r8a77990: Add drive-strengthWolfram Sang
According to R-Car Gen3 HW documentation 2.20 onwards, drive-strength is introduced to r8a77990. It is also documented for r8a774c0. Add it to the pinctrl driver. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220320092542.2308-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: Allow up to 10 fields for drive_regsWolfram Sang
Needed to support R-Car E3 and RZ/G2E drive regs. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220320092542.2308-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20pinctrl: renesas: checker: Rework drive and bias pin iterationGeert Uytterhoeven
The checker code to iterate over all drive strength and bias register description items is cumbersome, due to the repeated calculation of indices, and the use of hardcoded array sizes. The latter was done under the assumption they would never need to be changed, which turned out to be false. Increase readability by introducing helper macros to access drive strength and bias register description items. Increase maintainability by replacing hardcoded numbers by array sizes calculated at compile-time. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/5051ae56a1388ccf2d283dfc9624de2991cce914.1650355619.git.geert+renesas@glider.be
2022-04-19pinctrl: amd: Make the irqchip immutableMarc Zyngier
Prevent gpiolib from messing with the irqchip by advertising the irq_chip structure as immutable, making it const, and adding the various calls that gpiolib relies upon. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220419141846.598305-9-maz@kernel.org
2022-04-19pinctrl: msmgpio: Make the irqchip immutableMarc Zyngier
Prevent gpiolib from messing with the irqchip by advertising the irq_chip structure as immutable, making it const, and adding the various calls that gpiolib relies upon. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220419141846.598305-8-maz@kernel.org
2022-04-19pinctrl: apple-gpio: Make the irqchip immutableMarc Zyngier
Prevent gpiolib from messing with the irqchip by advertising the irq_chip structure as immutable, making it const, and adding the various calls that gpiolib relies upon. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220419141846.598305-7-maz@kernel.org
2022-04-19pinctrl: renesas: Simplify multiplication/shift logicGeert Uytterhoeven
"a * (1 << b)" == "a << b". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/31eaa3226c61ecf653e2b031307eea42a9a3d54e.1645460548.git.geert+renesas@glider.be
2022-04-18pinctrl: meson: Replace custom code by gpiochip_node_count() callAndy Shevchenko
Since we have generic function to count GPIO controller nodes under a given device, there is no need to open code it. Replace custom code by gpiochip_node_count() call. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2022-04-18pinctrl: meson: Enable COMPILE_TESTAndy Shevchenko
Enable COMPILE_TEST for a better test coverage. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2022-04-18pinctrl: meson: Rename REG_* to MESON_REG_*Andy Shevchenko
Currently compilation test fails on x86 due to name collision. The usual way to fix that is to move both conflicting parts to their own namespaces. Rename REG_* to MESON_REG_* as a prerequisite for enabling COMPILE_TEST. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2022-04-18pinctrl: armada-37xx: Reuse GPIO fwnode in armada_37xx_irqchip_register()Andy Shevchenko
Since we have fwnode of the first found GPIO controller assigned to the struct gpio_chip, we may reuse it in the armada_37xx_irqchip_register(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-04-18pinctrl: armada-37xx: Switch to use fwnode instead of of_nodeAndy Shevchenko
GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-04-18pinctrl: qcom: sm6350: fix order of UFS & SDC pinsLuca Weiss
In other places the SDC and UFS pins have been swapped but this was missed in the PINCTRL_PIN definitions. Fix that. Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20220318183004.858707-5-luca.weiss@fairphone.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-18pinctrl: pinctrl-aspeed-g6: add FWQSPI function-groupJohnny Huang
Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14) and FWSPIMISO (AB13). Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-5-quic_jaehyoo@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-18pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrlJae Hyun Yoo
FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove FWQSPID group in pinctrl. These pins must be used with the FWSPI pins that are dedicated for boot SPI interface which provides same 3.3v logic level. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-3-quic_jaehyoo@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-18pinctrl: mvebu: pinctrl driver for 98DX2530 SoCChris Packham
This pinctrl driver supports the 98DX25xx and 98DX35xx family of chips from Marvell. It is based on the Marvell SDK with additions for various (non-gpio) pin configurations based on the datasheet. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220414233055.586962-3-chris.packham@alliedtelesis.co.nz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-18pinctrl: qcom: sm8150: Specify PDC mapBhupesh Sharma
Specify the PDC mapping for SM8150, so that gpio interrupts are properly mapped to the wakeup IRQs of the PDC. Cc: Maulik Shah <quic_mkshah@quicinc.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220226184028.111566-3-bhupesh.sharma@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-14pinctrl: samsung: Switch to use for_each_gpiochip_node() helperAndy Shevchenko
Switch the code to use for_each_gpiochip_node() helper. While at it, in order to avoid additional churn in the future, switch to fwnode APIs where it makes sense. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-14pinctrl: samsung: Drop redundant node parameter in samsung_banks_of_node_get()Andy Shevchenko
The node is taken from the device pointer, which is supplied as a parameter, hence no need to have a separate parameter for node. Drop redundant node parameter in samsung_banks_of_node_get(). While at it, drop "of_" part in the samsung_banks_of_node_get() and samsung_banks_of_node_put() function names to avoid additional churn in the next changes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-13pinctrl: pinctrl-aspeed-g6: add FWQSPI function-groupJohnny Huang
Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14) and FWSPIMISO (AB13). Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220329173932.2588289-5-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley <joel@jms.id.au>
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-15 22:23:03 +0000