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2026-07-28drm/amd/display: Port DCN4+ MCIF ARB programming to new formatDillon Varone
[WHY&HOW] DML2.1 now outputs MCIF arbiter programming, but using a new structure. Change DCN401 and DCN42 to use this new format. Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fix use-after-free bugs in KUnit testsJohn Harrison
When running the KUnit tests with memory debugging enabled, a bunch of use-after-free errors are hit. These are due to using KUnit managed memory for the test objects but then giving them over to DRM managed objects. The KUnit stuff is deallocated first and when the DRM side calls its clean up helpers, it hits memory that has been freed already. NB: There is still a use-after-free bug in the writeback tests. However, fixing that requires driver side changes as well as test side changes. Those changes are part of: https://patchwork.freedesktop.org/series/152420/ Signed-off-by: John Harrison <John.Harrison@Igalia.com> CC: Alex Hung <alex.hung@amd.com> CC: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: share common DM KUnit helpersAlex Hung
Move fixture setup that was duplicated across several amdgpu_dm KUnit tests into amdgpu_dm_kunit_helpers.c: - dm_kunit_alloc_dc_with_ctx() allocates a dc and its dc_context. - dm_kunit_alloc_drm_with_connector_list() allocates a drm_device with an initialized connector list. Update the irq, psr, crtc and backlight tests to use these helpers. Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdkfd: Avoid topology_lock in kfd_mmapPhilip Yang
Use process-local GPU lookup in kfd_mmap() instead of kfd_device_by_id(), so mmap path does not take topology_lock while holding mmap_lock. Lockdep warning: possible circular locking dependency detected. Chain: &topology_lock -> &root->kernfs_rwsem -> &mm->mmap_lock Backtrace #0 (&topology_lock): down_read+0x8b/0x490 kfd_device_by_id+0x1d/0xf0 [amdgpu] kfd_mmap+0x11e/0x750 [amdgpu] __mmap_region+0x101f/0x25e0 mmap_region+0x228/0x2e0 do_mmap+0x9f2/0x1070 vm_mmap_pgoff+0x25d/0x430 Backtrace #1 (&root->kernfs_rwsem): down_write+0x80/0x200 kernfs_add_one+0x30/0x6a0 kernfs_create_dir_ns+0xd2/0x160 sysfs_create_dir_ns+0x12c/0x2a0 kobject_add_internal+0x280/0x8e0 kfd_topology_update_sysfs+0xb85/0x1970 [amdgpu] Backtrace #2 (&mm->mmap_lock): down_read_killable+0x8e/0x510 lock_mm_and_find_vma+0x299/0xb00 do_user_addr_fault+0x3fc/0xf80 exc_page_fault+0x73/0x110 filldir64+0x1aa/0x610 kernfs_fop_readdir+0x3c2/0x810 Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fix flip-done timeouts on mode1 resetLeo Li
The vblank on/off callbacks mixed use of amdgpu_irq_get/put() and amdgpu_dm_crtc_set_vupdate_irq() to enable and disable IRQs. With get/put, base driver will callback into DC to disable IRQs when refcount == 0. With set_vupdate_irq(), DC is called directly to disable IRQs, bypassing base driver's refcount tracking. During gpu reset, base driver can restore IRQs via amdgpu_irq_gpu_reset_resume_helper() > amdgpu_irq_update(). So if get/put() is not used (i.e. refcount == 0), then vupdate_irq will be disabled. This is problematic if DRM requests vblank on before amdgpu_irq_update() is called: drm_vblank_on() > set_vupdate_irq() enables vupdate_irq, but the refcount is still 0. gpu_reset_resume_helper() > irq_update() then immediately disables it, thus leading to flip done timeouts. This is made worse on DCN since VUPDATE_NO_LOCK is the only IRQ enabled. Prior to the "Fixes:" change, a combination of GRPH_FLIP and VSTARTUP IRQs were used, and they used get/put(). This explains why the change exposed this issue. Fix by using get/put() instead of set_vupdate_irq(). DCE is unchanged, since it relies on unbalanced enable/disable calls based on VRR status, and hence requires direct set_vupdate_irq(). Plus, it also uses GRPH_FLIP and VLINE IRQs, which are properly tracked by get/put(). Fixes: c87e6635d2db ("drm/amd/display: consolidate DCN vblank/flip handling onto vupdate_no_lock") Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/pm: fix torn gpu metrics readsYang Wang
amdgpu_dpm_get_gpu_metrics() returns a pointer to the shared metrics cache after dropping adev->pm.mutex. The sysfs path then copies from that pointer. Another reader can refresh the cache in place during the copy and return a snapshot containing data from two generations. Pass caller-provided storage through the DPM interface and copy the metrics while the mutex is held. This keeps the cache pointer private and makes each sysfs read observe one complete sample. Fixes: 25c933b1c4fc ("drm/amd/powerplay: add new sysfs interface for retrieving gpu metrics(V2)") Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/pm: fix pptable use-after-freeYang Wang
amdgpu_dpm_get_pp_table() returns a pointer to a driver-owned power table after dropping adev->pm.mutex. The sysfs path then copies from that pointer. A concurrent pp_table write can replace and free the allocation during the copy, causing a use-after-free. Change the DPM interface to copy into caller-provided storage while the mutex is held. Keep the size-only query for attribute discovery without exposing the driver-owned pointer. Fixes: 1684d3ba4885 ("drm/amd/amdgpu: change pptable output format from ASCII to binary") Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/ras: detect old ras eeprom formatTao Zhou
Handler of some formats will be implemented in the future. UMC_CHANNEL_IDX_V2 is a flag to indicate v2 format channel index stored in eeprom, the flag was retired in v3 and save_nps is introduced in v3, so they have no conflict. eeprom format v1: store channel index within a umc instance in eeprom range in UMC v12: 0 ~ 7 eeprom format v2: store global channel index in eeprom range in UMC v12: 0 ~ 127 v2: change the bit range of save_nps from [40:47] to [40:46], UMC_CHANNEL_IDX_V2 use bit 47. use RAS_DEV_WARN_RATELIMITED for retire record check, avoid log noise. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: convert ptl_hw_supported to enumVictor Zhao
Convert ptl_hw_supported to enum with three states: - AMDGPU_PTL_HW_UNINIT: not yet initialized - AMDGPU_PTL_HW_SUPPORTED: initialized and supported - AMDGPU_PTL_HW_NOT_SUPPORTED: initialized and not supported This allows skipping PTL initialization attempts when hardware is known to not support it, avoiding repeated initialization failures after GPU resets. v2:move ptl_hw_supported_state to AMDGPU_PTL_HW_NOT_SUPPORTED regardless of error code during first time initialization. Print init fail log when error code is not EOPNOTSUPP. Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: always get PTL state from PSP under sriovVictor Zhao
In SR-IOV mode, always query the latest PTL status from host via psp_performance_monitor_hw() to ensure the sysfs shows real-time hardware state. Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: add generic interfaces for PTL requests in virtualizationVictor Zhao
Add Performance Throttle Limiter (PTL) support for SR-IOV guest. Since VF cannot communicate with PSP directly at runtime in SR-IOV environment, use mailbox data fields to pass PTL parameters to PF, and parse response status from host mailbox registers. v2: - remove redundent checks - remove unused marco Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/ras: update flip bit setting for unirasTao Zhou
The flip bit setting is different if umc number is 8, only NPS1 and NPS2 are supported in this mode. Note: the typical value of umc number is 16, and it can only be 8 or 16 on umc v12. v2: if other umc number is encountered, default setting will be used. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: enable mode2 reset for SMU IP v15.0.5Kanala Ramalingeswara Reddy
Set the default reset method to mode2 for SMU 15.0.5. Signed-off-by: Kanala Ramalingeswara Reddy <Kanala.RamalingeswaraReddy@amd.com> Reviewed-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdkfd: fix uint32_t overflow in EOP ring buffer size alignmentWilliam Palacek
eop_ring_buffer_size in struct queue_properties is a u32. In kfd_queue_acquire_buffers() the expected EOP buffer size is computed as ALIGN(eop_ring_buffer_size, PAGE_SIZE); ALIGN uses typeof(x), so the addition is done in 32-bit. A user-supplied size of 0xFFFFF001 wraps to 0, causing kfd_queue_buffer_get() to skip its exact-size check (gated on size != 0) and accept any BO mapped at the address. On GFX8/GFX9 the MQD cp_hqd_eop_control is then programmed for an 8KB EOP ring backed by a 4KB BO, so CP EOP writes can land past the buffer and fault the GPU. Cast the operand to u64 so the alignment is computed in 64-bit; the size check in kfd_queue_buffer_get() then rejects the oversized request. Fixes: 42ea9cf2f16b ("drm/amdkfd: Relax size checking during queue buffer get") Signed-off-by: William Palacek <William.Palacek@amd.com> Reviewed-by: Alysa Liu <Alysa.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Fix NBIO 7.11.5 offsetsShubhankar Milind Sardeshpande
Fix NBIO 7.11.5 related offsets Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Enable support for PSP 15_0_5Shubhankar Milind Sardeshpande
Add PSP 15.0.5 related offsets for GFX to KMD interface and enable support for it. Co-developed-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdkfd: Fix missing authorization check in KFD_IOC_DBG_TRAP_DISABLEGang Ba
Prevent unauthorized termination of active GPU debug sessions. Previously, users with /dev/kfd access could terminate another process's debug session without proper ownership or ptrace authorization. Signed-off-by: Gang Ba <Gang.Ba@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: move debug_vm handling to amdgpu_cs_parser_finiPierre-Eric Pelloux-Prayer
The commit referenced below restarts the CS if the validation is still in progress. When debug_vm is enabled, all BOs from the CS are invalidated so we will hit an infinite loop. To avoid that, defer BO invalidation to amdgpu_cs_parser_fini. Fixes: 59720bfd8c6d ("drm/amdgpu: restart the CS if some parts of the VM are still invalidated") Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Update driver if header for SMU V15.0.5Kanala Ramalingeswara Reddy
Update smu v15.0.0 driver if header to be v15.0.5 compatible. Signed-off-by: Kanala Ramalingeswara Reddy <Kanala.RamalingeswaraReddy@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdkfd: Handle invalid event type in CRIU event restoreDavid Francis
In kfd_criu_restore_event, there was no handling for the event priv data having an invalid event type. The priv data here is untrusted and can be invalid. In that case, fail with EINVAL. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/ras: send RMA event in RAS init stageTao Zhou
Previously the event was only raised at runtime, also raise it during RAS init when threshold is exceeded and eeprom header is tagged bad, so we can get related cper at boot time. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Update message IDs to PMFW to correctly gather GFXOFF residency logsFares Soliman
Updates PPSMC_MSGs and set/get functions for gathering GFXOFF logs on Van Gogh. Logs are now gathered live rather than starting then stopping logging and reading an average value afterwards. This is in accordance to changes made in PMFW. In regards to messageID 0x52, the old interface uses a start/stop parameter, and the new one doesn't. The firmware is checked to determine which method to use. v2: added firmware guard to new interface, old interface kept as fallback Signed-off-by: Fares Soliman <Fares.Soliman@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Add missing MES helper parameter descriptionsSrinivasan Shanmugam
Complete the kernel-doc comments for the MES RS64 memory, process context, and gang context helper functions by documenting the missing function parameters to keep the kernel-doc comments consistent with their function signatures. Fixes: 56f7ea845e7d ("drm/amdgpu: add RS64 local memory context array init/fini") Fixes: cf5f98609a03 ("drm/amdgpu: add mes process context alloc/free") Fixes: 5ab89b491f21 ("drm/amdgpu: add mes gang contex alloc/free helper") Cc: Prike Liang <Prike.Liang@amd.com> Cc: Michael Chen <michael.chen@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fix writeback completion timingAlex Hung
[WHY] The out fence was signalled on the first vblank after arming, before the DMA finished copying, and the old code worked around this with an mdelay() in the IRQ handler. [HOW] Hold a vblank reference while writeback is pending and signal the out fence on the second vblank instead of using mdelay(). Add amdgpu_dm_crtc_complete_writeback() to finish and clean up writeback from both the IRQ and teardown paths. This can be verified by running IGT's kms_writeback 20 times without timeout errors. Assisted-by: Copilot:Claude-Opus-4.8 Signed-off-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Pack nested ucode_info structAlex Hung
Building for ARCH=um with W=1 C=1 makes the "amd_sriov_msg_vf2pf_info must be 1 KB" static assertion in amdgv_sriovmsg.h fail under sparse, exposed after UML builds were enabled. Sparse does not honor #pragma pack(push, 1) for the nested ucode_info struct, so it sizes each element as 8 bytes instead of 5 and computes the surrounding structure as larger than 1 KB. The compilers get this right via the enclosing pragma, but the annotation should be explicit. Fixes: af3f2f5db265 ("drm/amdgpu: Remove UML build exclusion from Kconfig") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202607091659.SHEscT0c-lkp@intel.com/ Cc: Harry Wentland <harry.wentland@amd.com> Assisted-by: Copilot:Claude-Opus-4.8 Signed-off-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Fix __rcu fence pointer accessesAlex Hung
Building for ARCH=um with W=1 C=1 makes sparse report "incompatible types in comparison expression (different address spaces)" warnings in the KFD code, exposed after UML builds were enabled: - amdgpu_amdkfd_fence.c compares the __rcu-annotated dma_fence.ops pointer directly in to_amdgpu_amdkfd_fence(). - amdgpu_amdkfd_gpuvm.c compares the __rcu eviction fence pointer directly in amdgpu_amdkfd_gpuvm_restore_process_bos(). Fixes: af3f2f5db265 ("drm/amdgpu: Remove UML build exclusion from Kconfig") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202607091659.SHEscT0c-lkp@intel.com/ Cc: Harry Wentland <harry.wentland@amd.com> Assisted-by: Copilot:Claude-Opus-4.8 Signed-off-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdkfd: fix QID bit leak in pqm_create_queue()Vladimir Marioukhine
When MES is enabled and amdgpu_amdkfd_alloc_kernel_mem() fails during the first queue creation for a process, pqm_create_queue() returns early via 'return retval' without going through the err_create_queue cleanup label. This means clear_bit(*qid, pqm->queue_slot_bitmap) is never called, leaving the reserved QID bit permanently set in queue_slot_bitmap. Over time this leaks QID slots, potentially exhausting all available queue slots. Fix this by replacing 'return retval' with 'goto err_allocate_pqn' so that clear_bit() is always called on the error path without touching the uninitialized pqn pointer. AILIKFD-813 Reported-by: Deucher, Alexander <alexander.deucher@amd.com> Signed-off-by: Vladimir Marioukhine <Vladimir.Marioukhine@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Drop vm_manager PASID to VM mappingSrinivasan Shanmugam
VM lookup users now resolve DRM PASIDs through the global PASID xarray: PASID -> fpriv -> VM The per-device vm_manager.pasids xarray is no longer needed. Remove PASID registration and removal from the VM init/fini paths, drop vm_manager PASID initialization/cleanup, and remove the xarray from struct amdgpu_vm_manager. The PASID is allocated only after amdgpu_vm_init() completes, so the initializer no longer consumes or assigns a PASID. Remove the now-unused argument while keeping vm->pasid as per-VM state for TLB flushes and other hardware programming paths. v6: - Remove the now-unused PASID argument from amdgpu_vm_init(). - Remove the related vm->pasid assignment and error-path reset from VM init. - Keep vm->pasid in struct amdgpu_vm for existing hardware users. Cc: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Promote DC to 3.2.390Taimur Hassan
This DC patchset brings improvements in multiple areas. In summary, we have: * Unified dc_update_state commit interface with dc_probe model, dc_state_get_status, and perfmon BLS sequence * DCN42 enhancements including mcache programming, PMFW DF C-state client, and DCCG clocking fix * DML2.1 writeback validation plus MCIF ARB and watermark/latency updates * Color management refactor to dc_plane_cm with plane/CRTC colorop test coverage * Greatly enhanced KUnit coverage across amdgpu_dm, connector, CRC, DMUB, and color management * HDMI AV mute timing, DP link training logging, and Apple Studio Display fixes * Code cleanup including DCE trim from DCN-only builds and HWSS refactors Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add SPL UPSP upsampling and YUV422 scaling supportWayne Lin
- Add YUV422/YUV444 pixel format definitions - Handle YUV422 chroma scaling ratios - Use separate horizontal and vertical viewport divisors - Add UPSP upsampling register programming - Refine tap selection for horizontally and vertically subsampled formats Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Flush IRQ workqueue in schedule-work testsAlex Hung
[WHAT] The tests dm_test_irq_schedule_work_queues_handler, dm_test_irq_schedule_work_requeue_fallback, and dm_test_irq_handler_dispatches_work relied on amdgpu_dm_irq_fini() running each pending low-context work item before freeing the handlers, and only checked the handler counts afterwards. amdgpu_dm_irq_fini() now cancels pending work with cancel_work_sync() instead of flushing it, so work that has not yet started never runs and the counts stay below the expected values, failing the tests. Flush the private DM IRQ workqueue (adev->dm.irq_wq) so the scheduled handlers complete, check the counts, then tear down. Flushing this driver-owned workqueue is allowed, unlike the system-wide workqueues. Fixes: 0d6453fd6e17 ("drm/amd/display: Fix DM IRQ teardown races") Cc: Geoffrey McRae <geoffrey.mcrae@amd.com> Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fix missing dc_3dlut forward declarationAlex Hung
[WHY] The __set_colorop_3dlut() prototype in the KUnit-test section of amdgpu_dm_color.h references struct dc_3dlut, but no forward declaration for that struct exists in the header. The forward declaration was originally present but was repurposed into struct dc_plane_cm when the adjacent amdgpu_dm_atomic_lut3d() prototype was updated, leaving __set_colorop_3dlut() without a declaration for struct dc_3dlut. [HOW] Add back forward declaration of struct dc_3dlut alongside the other forward declarations at the top of the header. Fixes: b008c67efb36 ("drm/amd/display: Introduce dc_plane_cm and migrate surface update color path") Cc: Alex Hung <alex.hung@amd.com> Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add DCHUBBUB_HW_DEBUG offset/maskMatthew Stewart
Add missing register defines for DCN42B. Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Reduce DML reinitialization when params don't changeClara Wong
[WHY] Reinitializing DML causes an extra ~8s delay in gaming mode preset switches on some systems [HOW] Don't reinitialize DML unless params/caps have changed Reviewed-by: Austin Zheng <austin.zheng@amd.com> Reviewed-by: Taimur Hassan <syed.hassan@amd.com> Signed-off-by: Clara Wong <Clara.Wong@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: hide Apple Studio Display secondary tileJerry Zuo
The Apple Studio Display exposes a 2x1 tiled panel over two SST DP links. The primary tile advertises the full 5120x2880 mode (with DSC on the bandwidth-sufficient link) while the secondary carries a per-tile 2560x2880 timing on a link without sufficient bandwidth. Report the non-primary tile connector as disconnected during detect so compositors only see the primary DP link and configure a single 5K mode instead of driving both tiled streams independently. Drive the behaviour from an EDID quirk: add a disable_second_tile panel patch that apply_edid_quirks() sets for the affected Apple Studio Display panel IDs (0xAE3A, 0xAE42, 0xAE46), and have detect() hide the secondary tile when the sink carries that quirk. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Register DCN as a PMFW DF C-state client on DCN42Leo Chen
[Why] DCN must not gate DF C-state locally via the DCHUBBUB ALLOW_SELF_REFRESH controls: forcing a local "disallow" during MM-stutter re-entry can wedge the fabric and hang boot. When DCN is disallowing c-state or has invalid watermarks we should be explicit about it rather than using the watermark force selector. [How] Register DCN as a client of PMFW's DF C-state arbiter and signal over DALSMC whether DCN permits DF C-state; PMFW allows DF C-state only once every client (including DCN) has voted "allow". - dc_clocks.cstate_allow: last DCN vote acked by PMFW - clk_mgr_funcs::notify_cstate_disable(clk_mgr, disable) prepare_bandwidth and headless dc_power_down_on_boot vote Allow; hardware_release votes Disallow; init_clocks (D0 entry) only clears the cache (cstate_allow) so the next allow re-syncs with PMFW. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Make dc_state_update const in commit pathWenjing Liu
[Why] The state-update commit path only reads the caller's update descriptor, it never mutates the dc_state_update root. Making the pointer const documents that contract. [How] Add const to the updates parameter of dc_update_state and dc_check_state_update. Mark the single-assignment locals in dc_update_state_init const and replace the memset plus field-by-field assignment with a compound literal initializer. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Wire probe commit path into dc_update_stateWenjing Liu
[Why] The dc_update_state commit interface and the dc_probe object model existed but were not connected: there was no path to validate, commit, and program a probe through the update pipeline, nor to read the result back. The measurement waits on OTG frame edges and must not block fast updates. [How] - Move the per-commit scratch off dc_stream_state onto a dc-owned pool; acquire at init, release on cleanup or prepare failure, serialized by the DM global lock every commit path already holds. - dc_update_state drives stream commits, probe-only commits, or both through one staged init/prepare/execute/cleanup loop with a null-arg guard. prepare releases the scratch slot on failure; cleanup releases it on success. - Probe prepare installs the absolute probe set in place; execute calls the perfmon programming hook in the unlocked window and latches results. - Add resource_validate_probe_set, a context-free achievability check shared by dc_validate_global_state (full update) and probe prepare (probe-only). - dc_state_get_status gains a probe status class with a probe filter and a by-type mapping; dc_validation_set gains probes/probe_count. Drop the dead actual_* fields from struct dc_qos_info. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Introduce program_perfmon hwss hook and BLS perfmon sequenceWenjing Liu
[Why] The hubbub perfmon peak-bandwidth path used a monolithic function combining counter configuration and enable in one call, and wrote results into a caller-supplied struct outside the dc_state model. A BLS-driven approach builds the measurement from stateless primitives, gates it to OTG frame boundaries, and stores results in dc_state. [How] - Rename the peak-BW vtable members from "unbounded_bandwidth" to "out_of_order_bandwidth" and split them into arm and start operations. - Add the full set of perfmon BLS primitives - param structs, union members, enum entries, executors, and hwss_add_* builders - for reset, arm, every start_measuring_* and every get_* operation. - Add dc_probe_status (valid, type, result union) plus probe_status[] to dc_state. - Replace the measure_memory_qos hook with program_perfmon(dc, context), which writes results into probe_status[]. - dc_get_qos_info no longer calls the removed hook. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Introduce dc_state_get_status unified status accessorWenjing Liu
[Why] dc_state_get_stream_status() is typed against streams only, leaving no extensible slot for future status classes. The public status accessor signature needs to stay stable as new status classes are added. [How] Add a dc_get_status_type bitmask and the dc_get_status_options / dc_state_status structs. Implement dc_state_get_status() to populate the output object per the options bitmask, and make dc_state_get_stream_status() a shim over it. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Refactor dc_validation_set array into single root structWenjing Liu
[Why] dc_validate_with_context() took a C array of per-stream elements plus a separate count. This flat array cannot be extended to carry global objects without widening the signature further. [How] Rename the per-stream element to dc_validation_stream, and make dc_validation_set a root struct holding streams[MAX_STREAMS] and stream_count. Update dc_validate_with_context() to take a single const dc_validation_set * and propagate the new shape through all DC-layer callers and helpers. Remove the never-implemented dce112_validate_with_context declaration and the orphaned dce100 forward-declare. No behavior change. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Introduce dc_update_state unified commit interfaceWenjing Liu
[Why] dc_update_planes_and_stream() is typed against surface/stream arrays only, leaving no extensible slot for future object classes. The public entry point names and signatures need to stay stable as new object classes are added. [How] Introduce dc_update_state() and dc_check_state_update(), both taking a dc_state_update root object. dc_update_state() routes stream and plane updates through the existing pipeline. Keep dc_update_planes_and_stream() and dc_check_update_surfaces_for_stream() as shims that delegate. Change dc_update_state_init() to take a const dc_state_update* and rename dc_update_planes_and_stream_{init,prepare,execute,cleanup} -> dc_update_state_{init,prepare,execute,cleanup}. Rename surface_update_type -> dc_update_type and surface_update_descriptor -> dc_update_descriptor. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Introduce dc_probe public object modelWenjing Liu
[Why] Performance measurement needs to commit through the same update entry point as planes and streams, with DM working against an abstraction of what to measure rather than the hardware block that performs it. [How] Add dc_probe.h defining dc_probe_type (the measurable quantity), dc_probe_target_state (not measuring / measuring / measured), dc_probe_scope (global only, per-stream/plane deferred), and dc_probe_state (an inline descriptor with copy semantics, no refcount). dc_state carries the committed set as probes[MAX_PROBES] plus probe_count. dc_state_update carries dc_probe_updates as the desired absolute set that DC diffs against the committed set. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Revert Fix DMSS not triggering for HDR to SDR transitionJustin Chen
Reverting this commit as it causes a regression lighting up eDP panels: This reverts commit 1f07e9fddc4a ("drm/amd/display: Fix DMSS not triggering for HDR to SDR transition") Fixes: 1f07e9fddc4a ("drm/amd/display: Fix DMSS not triggering for HDR to SDR transition") Reviewed-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Yihan Zhu <yihan.zhu@amd.com> Signed-off-by: Justin Chen <Justin.Chen5@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Adjust structure dml2_display_dlg_regsAurabindo Pillai
Adjust structure dml2_display_dlg_regs for future use Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add stream validation tests for connectorBhawanpreet Lakha
Add KUnit coverage for amdgpu_dm_create_validate_stream_for_sink() and amdgpu_dm_connector_funcs_update_after_detect(): null dm_state, MST no-op, and unchanged sink handling. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add mode validation and CEC tests for connectorBhawanpreet Lakha
Add KUnit coverage for connector mode validation and HDMI CEC: mode_valid rejects interlaced and doublescan modes, set_edid with no notifier, and the S3 suspend/resume CEC handlers. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add i2c and EDID parsing tests for connectorBhawanpreet Lakha
Add KUnit coverage for the i2c and EDID parsing helpers: amdgpu_dm_i2c_func(), amdgpu_dm_i2c_xfer(), get_amd_vsdb(), parse_hdmi_amd_vsdb() and parse_edid_displayid_vrr(). Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add mode helper tests for connectorBhawanpreet Lakha
Add KUnit coverage for the connector mode helpers: amdgpu_dm_connector_funcs_force(), dm_validate_stream_and_context(), amdgpu_dm_connector_to_encoder(), amdgpu_dm_get_native_mode(), amdgpu_dm_create_common_mode(), amdgpu_dm_connector_add_common_modes(), amdgpu_dm_connector_ddc_get_modes(), add_fs_modes() and amdgpu_dm_connector_add_freesync_modes(). Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Adjust the structure dml2_dchub_watermark_regsAurabindo Pillai
Adjust the structure dml2_dchub_watermark_regs for future usage Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-07 05:05:12 +0000