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2023-04-26drm/i915/mtl: Implement Wa_14019141245Radhakrishna Sripada
Enable strict RAR to prevent spurious GPU hangs. v1.1: Rebase Bspec: 51762 Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230425183011.865085-1-radhakrishna.sripada@intel.com
2023-04-26drm/i915/hwmon: Block waiting for GuC reset to completeAshutosh Dixit
Instead of erroring out when GuC reset is in progress, block waiting for GuC reset to complete which is a more reasonable uapi behavior. v2: Avoid race between wake_up_all and waiting for wakeup (Rodrigo) v3: Remove timeout when blocked (Tvrtko) Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230420164041.1428455-4-ashutosh.dixit@intel.com
2023-04-26drm/i915/guc: Disable PL1 power limit when loading GuC firmwareAshutosh Dixit
On dGfx, the PL1 power limit being enabled and set to a low value results in a low GPU operating freq. It also negates the freq raise operation which is done before GuC firmware load. As a result GuC firmware load can time out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power limit was enabled and set to a low value). Therefore disable the PL1 power limit when allowed by HW when loading GuC firmware. v2: - Take mutex (to disallow writes to power1_max) across GuC reset/fw load - Add hwm_power_max_restore to error return code path v3 (Jani N): - Add/remove explanatory comments - Function renames - Type corrections - Locking annotation v4: - Don't hold the lock across GuC reset (Rodrigo) - New locking scheme (suggested by Rodrigo) - Eliminate rpm_get in power_max_disable/restore, not needed (Tvrtko) v5: - Fix uninitialized pl1en variable compile warning reported by kernel build robot by creating new err_rps label Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062 Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230420164041.1428455-3-ashutosh.dixit@intel.com
2023-04-26drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_writeAshutosh Dixit
In preparation for follow-on patches, refactor hwm_power_max_write to take hwmon_lock and runtime pm wakeref at start of the function and release them at the end, therefore acquiring these just once each. Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230420164041.1428455-2-ashutosh.dixit@intel.com
2023-04-26drm/i915/mtl: Add the missing CPU transcoder mask in intel_device_infoRadhakrishna Sripada
CPU transcoder mask is used to iterate over the available CPU transcoders in the macro for_each_cpu_transcoder(). The macro is broken on MTL and got highlighted when audio state was being tracked for each transcoder added in [1]. Add the missing CPU transcoder mask which is similar to ADL-P mask but without DSI transcoders. [1]: https://patchwork.freedesktop.org/patch/523723/ Fixes: 7835303982d1 ("drm/i915/mtl: Add MeteorLake PCI IDs") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Acked-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230420221248.2511314-1-radhakrishna.sripada@intel.com
2023-04-26drm/vkms: allow full alpha blending on all planesMaíra Canal
Before commit bc0d7fdefec6 ("drm: vkms: Supports to the case where primary plane doesn't match the CRTC"), the composition was executed on top of the primary plane. Therefore, the primary plane was not able to support the alpha channel. After commit bc0d7fdefec6, this is possible, as the composition is now executed on top of the CRTC. So, allow all planes to support the alpha channel, making full alpha blending possible in vkms. Signed-off-by: Maíra Canal <mcanal@igalia.com> Reviewed-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Arthur Grillo <arthurgrillo@riseup.net> Signed-off-by: Maíra Canal <mairacanal@riseup.net> Link: https://patchwork.freedesktop.org/patch/msgid/20230420232228.273340-1-mcanal@igalia.com
2023-04-26drm/i915/guc: Actually return an error if GuC version range check failsJohn Harrison
Dan Carpenter pointed out that 'err' was not being set in the case where the GuC firmware version range check fails. Fix that. Note that while this is a bug fix for a previous patch (see Fixes tag below). It is an exceedingly low risk bug. The range check is asserting that the GuC firmware version is within spec. So it should not be possible to ever have a firmware file that fails this check. If larger version numbers are required in the future, that would be a backwards breaking spec change and thus require a major version bump, in which case an old i915 driver would not load that new version anyway. Fixes: 9bbba0667f37 ("drm/i915/guc: Use GuC submission API version number") Reported-by: Dan Carpenter <error27@gmail.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230421224742.2357198-1-John.C.Harrison@Intel.com
2023-04-26Merge tag 'flex-array-transformations-6.4-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux Pull flexible-array updates from Gustavo Silva: "Transform more zero-length and one-element arrays into C99 flexible-array members" * tag 'flex-array-transformations-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux: uapi: net: ipv6: Replace fake flex-array with flex-array member drm/vmwgfx: Replace one-element array with flexible-array member ASoC: uapi: Replace zero-length arrays with __DECLARE_FLEX_ARRAY() helper
2023-04-25Merge tag 'acpi-6.4-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull ACPI updates from Rafael Wysocki: "These update the ACPICA code in the kernel to upstream revision 20230331, fix the ACPI SBS driver and the evaluation of the _PDC method on Xen dom0 in the ACPI processor driver, update the ACPI driver for Intel SoCs and clean up code in multiple places. Specifics: - Update the ACPICA code in the kernel to upstream revision 20230331 including the following changes: * Delete bogus node_array array of pointers from AEST table (Jessica Clarke) * Add support for trace buffer extension in GICC to the ACPI MADT parser (Xiongfeng Wang) * Add missing macro ACPI_FUNCTION_TRACE() for acpi_ns_repair_HID() (Xiongfeng Wang) * Add missing tables to astable (Pedro Falcato) * Add support for 64 bit loong_arch compilation to ACPICA (Huacai Chen) * Add support for ASPT table in disassembler to ACPICA (Jeremi Piotrowski) * Add support for Arm's MPAM ACPI table version 2 (Hesham Almatary) * Update all copyrights/signons in ACPICA to 2023 (Bob Moore) * Add support for ClockInput resource (v6.5) (Niyas Sait) * Add RISC-V INTC interrupt controller definition to the list of supported interrupt controllers for MADT (Sunil V L) * Add structure definitions for the RISC-V RHCT ACPI table (Sunil V L) * Address several cases in which the ACPICA code might lead to undefined behavior (Tamir Duberstein) * Make ACPICA code support flexible arrays properly (Kees Cook) * Check null return of ACPI_ALLOCATE_ZEROED in acpi_db_display_objects() (void0red) * Add os specific support for Zephyr RTOS to ACPICA (Najumon) * Update version to 20230331 (Bob Moore) - Fix evaluating the _PDC ACPI control method when running as Xen dom0 (Roger Pau Monne) - Use platform devices to load ACPI PPC and PCC drivers (Petr Pavlu) - Check for null return of devm_kzalloc() in fch_misc_setup() (Kang Chen) - Log a message if enable_irq_wake() fails for the ACPI SCI (Simon Gaiser) - Initialize the correct IOMMU fwspec while parsing ACPI VIOT (Jean-Philippe Brucker) - Amend indentation and prefix error messages with FW_BUG in the ACPI SPCR parsing code (Andy Shevchenko) - Enable ACPI sysfs support for CCEL records (Kuppuswamy Sathyanarayanan) - Make the APEI error injection code warn on invalid arguments when explicitly indicated by platform (Shuai Xue) - Add CXL error types to the error injection code in APEI (Tony Luck) - Refactor acpi_data_prop_read_single() (Andy Shevchenko) - Fix two issues in the ACPI SBS driver (Armin Wolf) - Replace ternary operator with min_t() in the generic ACPI thermal zone driver (Jiangshan Yi) - Ensure that ACPI notify handlers are not running after removal and clean up code in acpi_sb_notify() (Rafael Wysocki) - Remove register_backlight_delay module option and code and remove quirks for false-positive backlight control support advertised on desktop boards (Hans de Goede) - Replace irqdomain.h include with struct declarations in ACPI headers and update several pieces of code previously including of.h implicitly through those headers (Rob Herring) - Fix acpi_evaluate_dsm_typed() redefinition error (Kiran K) - Update the pm_profile sysfs attribute documentation (Rafael Wysocki) - Add 80862289 ACPI _HID for second PWM controller on Cherry Trail to the ACPI driver for Intel SoCs (Hans de Goede)" * tag 'acpi-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (64 commits) ACPI: LPSS: Add 80862289 ACPI _HID for second PWM controller on Cherry Trail ACPI: bus: Ensure that notify handlers are not running after removal ACPI: bus: Add missing braces to acpi_sb_notify() ACPI: video: Remove desktops without backlight DMI quirks ACPI: video: Remove register_backlight_delay module option and code ACPI: Replace irqdomain.h include with struct declarations fpga: lattice-sysconfig-spi: Add explicit include for of.h tpm: atmel: Add explicit include for of.h virtio-mmio: Add explicit include for of.h pata: ixp4xx: Add explicit include for of.h ata: pata_macio: Add explicit include of irqdomain.h serial: 8250_tegra: Add explicit include for of.h net: rfkill-gpio: Add explicit include for of.h staging: iio: resolver: ad2s1210: Add explicit include for of.h iio: adc: ad7292: Add explicit include for of.h ACPICA: Update version to 20230331 ACPICA: add os specific support for Zephyr RTOS ACPICA: ACPICA: check null return of ACPI_ALLOCATE_ZEROED in acpi_db_display_objects ACPICA: acpi_resource_irq: Replace 1-element arrays with flexible array ACPICA: acpi_madt_oem_data: Fix flexible array member definition ...
2023-04-25Merge tag 'drm-next-2023-04-24' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
Pull drm updates from Dave Airlie: "There is a new Qualcomm accel driver for their QAIC, dma-fence got a deadline feature added, lots of refactoring around fbdev emulation, and the usual pre-release hw enablements from AMD and Intel and fixes everywhere. New drivers: - add QAIC acceleration driver dma-buf: - constify kobj_type structs - Reject prime DMA-Buf attachment if get_sg_table is missing. fbdev: - cmdline parser fixes - implement fbdev emulation for GEM DMA drivers - always use shadow buffer in fbdev emulation helpers dma-fence: - add deadline hint to fences - signal private stub fence core: - improve DisplayID 2.0 and EDID parsing - add gem eviction function + callback - prep to convert shmem helper to GEM resv lock - move suballocator from radeon/amdgpu to core for Xe - HPD polling fixes - Documentation improvements - Add atomic enable_plane callback - use tgid instead of pid for client tracking - DP: Add SDP Error Detection Configuration Register - Add prime import/export to vram-helper - use pci aperture helpers in more drivers panel: - Radxa 8/10HD support - Samsung AMD495QA01 support - Elida KD50T048A - Sony TD4353 - Novatek NT36523 - STARRY 2081101QFH032011-53G - B133UAN01.0 - AUO NE135FBM-N41 i915: - More MTL enabling - fix s/r problems with MEI/PXP - Implement fb_dirty for PSR,FBC,DRRS fixes - Fix eDP+DSI dual panel systems - Fix issue #6333: "list_add corruption" and full system lockup from performance monitoring - Don't use stolen memory or BAR for ring buffers on LLC platforms - Make sure DSM size has correct 1MiB granularity on Gen12+ - Whitelist COMMON_SLICE_CHICKEN3 for UMD access on Gen12+ - Add engine TLB invalidation for Meteorlake - Fix GSC races on driver load/unload on Meteorlake+ - Make kobj_type structures constant - Move fd_install after last use of fence - wm/vblank refactoring - display code refactoring - Create GSC submission targeting HDCP and PXP usages on MTL+ - Enable HDCP2.x via GSC CS - Fix context runtime accounting on sysfs fdinfo for heavy workloads - Use i915 instead of dev_priv insied the file_priv structure - Replace fake flex-array with flexible-array member amdgpu: - Make kobj structures const - Generalize dmabuf import to work with KFD - Add capped/uncapped workload handling for supported APUs - Expose additional memory stats via fdinfo - Register vga_switcheroo for apple-gmux - Initial NBIO7.9, GC 9.4.3, GFXHUB 1.2, MMHUB 1.8 support - Initial DC FAM infrastructure - Link DC backlight to connector device rather than PCI device - Add sysfs nodes for secondary VCN clocks amdkfd: - Make kobj structures const - Support for exporting buffers via dmabuf - Multi-VMA page migration fixes - initial GC 9.4.3 support radeon: - iMac fix - convert to client based fbdev emulation habanalabs: - Add opcodes to the CS ioctl to allow user to stall/resume specific engines inside Gaudi2. - INFO ioctl the amount of device memory that the driver and f/w reserve for themselves. - INFO ioctl a bit-mask of the available rotator engines - INFO ioctl the register's address of the f/w that should be used to trigger interrupts - INFO ioctl two new opcodes to fetch information on h/w and f/w events - Enable graceful reset mechanism for compute-reset. - Align to the latest firmware specs. - Enforce the release order of the compute device and dma-buf. msm: - UBWC decoder programming rework - SM8550, SM8450 bindings update - uapi C++ fix - a3xx and a4xx devfreq support - GPU and GEM updates to avoid allocations which could trigger reclaim (shrinker) in fence signaling path - dma-fence deadline hint support and wait-boost - a640/650 speed bin support cirrus: - convert to regular atomic helpers - add damage clipping mediatek: - 10-bit overlay support - mt8195 support - Only trigger DRM HPD events if bridge is attached - Change the aux retries times when receiving AUX_DEFER rockchip: - add 4K support vc4: - use drm_gem_objects virtio: - allow KMS support to be disabled - add damage clipping vmwgfx: - buffer object lifetime fixes exynos: - move MIPI DSI driver to drm bridge for iMX sharing - use kernel fbdev emulation panfrost: - add support for mali MT81xx devices - add speed binning support lima: - add usage stats tegra: - fbdev client conversion vkms: - Add primary plane positioning support" * tag 'drm-next-2023-04-24' of git://anongit.freedesktop.org/drm/drm: (1495 commits) drm/i915/dp_mst: Fix active port PLL selection for secondary MST streams drm/exynos: Implement fbdev emulation as in-kernel client drm/exynos: Initialize fbdev DRM client drm/exynos: Remove fb_helper from struct exynos_drm_private drm/exynos: Remove struct exynos_drm_fbdev drm/exynos: Remove exynos_gem from struct exynos_drm_fbdev drm/i915: Fix memory leaks in i915 selftests drm/i915: Make intel_get_crtc_new_encoder() less oopsy drm/i915/gt: Avoid out-of-bounds access when loading HuC drm/amdgpu: add some basic elements for multiple XCD case drm/amdgpu: move vmhub out of amdgpu_ring_funcs (v4) Revert "drm/amdgpu: enable ras for mp0 v13_0_10 on SRIOV" drm/amdgpu: add common ip block for GC 9.4.3 drm/amd/display: Add logging when DP link training Clock recovery is Successful drm/amdgpu: add common early init support for GC 9.4.3 drm/amdgpu: switch to v9_4_3 gfx_funcs callbacks for GC 9.4.3 drm/amd/display: Add logging when setting DP sink power state fails drm/amdkfd: Add gfx_target_version for GC 9.4.3 drm/amdkfd: Enable HW_UPDATE_RPTR on GC 9.4.3 drm/amdgpu: reserve the old gc_11_0_*_mes.bin ...
2023-04-25drm/i915/mtl: Add workaround 14018778641Tejas Upadhyay
WA 18018781329 is applicable now across all MTL steppings. V2: - Remove IS_MTL check, code already running for MTL - Matt Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230424101749.3719600-1-tejas.upadhyay@intel.com
2023-04-25drm/i915/selftest: Record GT error for gt failureTejas Upadhyay
igt_live_test has pr_err dumped in case of some GT failures. It will be more informative regarding GT if we use gt_err instead. Cc: Andi Shyti <andi.shyti@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230424133607.3736825-1-tejas.upadhyay@intel.com
2023-04-25drm/i915/adlp+: Disable DC5/6 states for TC port DDI/AUX and for combo port AUXImre Deak
On ADLP+ Bspec allows DC5/6 to be enabled while power well 2 is enabled. Since the AUX and DDI power wells (except for port A/B) are also backed by power well 2, this would suggest that DC5/6 can be enabled while any of these AUX or DDI port functionalities are used. As opposed to this AUX transfers will time out on ADLP TypeC ports while DC6 is enabled. Until the restriction for DC5/6 is clarified in Bspec let's assume that the intention is to allow for using these power states while pipe A/B is enabled, but only for combo ports which can be used with eDP outputs. Similarly assume that AUX transaction initiated by the driver on any port requires DC states to be disabled. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Fixes: 88c487938414 ("drm/i915: Use separate "DC off" power well for ADL-P and DG2") Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230424200205.1732941-1-imre.deak@intel.com
2023-04-25drm/bridge: tc358768: Add atomic_get_input_bus_fmts() implementationFrancesco Dolcini
Add atomic_get_input_bus_fmts() implementation, tc358768 has a parallel RGB input interface with the actual bus format depending on the amount of parallel input data lines. Without this change when the tc358768 is used with less than 24bit the color mapping is completely wrong. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Robert Foss <rfoss@kernel.org> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230330095941.428122-7-francesco@dolcini.it
2023-04-25drm/vc4: hdmi: Add BT.2020 SupportDave Stevenson
Even though we report that we support the BT.2020 Colorspace, we were always using the BT.709 conversion matrices. Let's add the BT.2020 ones. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20221207-rpi-hdmi-improvements-v3-9-bdd54f66884e@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2023-04-25drm/vc4: hdmi: Add BT.601 SupportDave Stevenson
Even though we report that we support the BT601 Colorspace, we were always using the BT.709 conversion matrices. Let's add the BT601 ones. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20221207-rpi-hdmi-improvements-v3-8-bdd54f66884e@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2023-04-25drm/vc4: hdmi: Add a function to retrieve the CSC matrixDave Stevenson
The CSC matrix to use depends on the output format, its range and the colorspace. Since we're going to add more colorspaces, let's move the CSC matrix retrieval to a function. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20221207-rpi-hdmi-improvements-v3-7-bdd54f66884e@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2023-04-25drm/vc4: hdmi: Rework the CSC matrices organizationDave Stevenson
The CSC matrices were stored as separate matrix for each colorspace, and if we wanted a limited or full RGB output. This created some gaps in our support and we would not always pick the relevant matrix. Let's rework our data structure to store one per colorspace, and then a matrix for limited range and one for full range. This makes us add a new matrix to support full range BT709 YUV output. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20221207-rpi-hdmi-improvements-v3-6-bdd54f66884e@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2023-04-25drm/vc4: hdmi: Swap CSC matrix channels for YUV444Dave Stevenson
YUV444 and YUV422 actually require the same matrix, but programmed differently. We've dealt with it in the past by having two matrices, with the one for YUV444 reordered to accomodate the hardware. This gets in the way of subsequent reworks so let's define a function that will take the coefficients swap into account, and remove the now redundant YUV444 matrix. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20221207-rpi-hdmi-improvements-v3-5-bdd54f66884e@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2023-04-25drm/vc4: hdmi: Rename full range helperDave Stevenson
The VC4 HDMI driver has a helper function to figure out whether full range or limited range RGB is being used called vc4_hdmi_is_full_range_rgb(). We'll need it to support other colorspaces, so let's rename it to vc4_hdmi_is_full_range(). Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20221207-rpi-hdmi-improvements-v3-4-bdd54f66884e@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2023-04-25drm/vc4: hdmi: Add Broadcast RGB property to allow override of RGB rangeDave Stevenson
Copy Intel's "Broadcast RGB" property semantics to add manual override of the HDMI pixel range for monitors that don't abide by the content of the AVI Infoframe. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Reviewed-by: Hans Verkuil <hverkuil-cisco at xs4all.nl> Link: https://lore.kernel.org/r/20221207-rpi-hdmi-improvements-v3-3-bdd54f66884e@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2023-04-25drm/vc4: hdmi: Update all the planes if the TV margins are changedMaxime Ripard
On VC4, the TV margins on the HDMI connector are implemented by scaling the planes. However, if only the TV margins or the connector are changed by a new state, the planes ending up on that connector won't be. Thus, they won't be updated properly and we'll effectively ignore that change until the next commit affecting these planes. Let's make sure to add all the planes attached to the connector so that we can update them properly. Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20221207-rpi-hdmi-improvements-v3-2-bdd54f66884e@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2023-04-25drm/vc4: Switch to container_of_constMaxime Ripard
container_of_const() allows to preserve the pointer constness and is thus more flexible than inline functions. Let's switch all our instances of container_of() to container_of_const(). Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20221207-rpi-hdmi-improvements-v3-1-bdd54f66884e@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2023-04-25drm/i915/mtl: workaround coherency issue for MediaFei Yang
This patch implements Wa_22016122933. In MTL, memory writes initiated by the Media tile update the whole cache line, even for partial writes. This creates a coherency problem for cacheable memory if both CPU and GPU are writing data to different locations within a single cache line. This patch circumvents the issue by making CPU/GPU shared memory uncacheable (WC on CPU side, and PAT index 2 for GPU). Additionally, it ensures that CPU writes are visible to the GPU with an intel_guc_write_barrier(). While fixing the CTB issue, we noticed some random GSC firmware loading failure because the share buffers are cacheable (WB) on CPU side but uncached on GPU side. To fix these issues we need to map such shared buffers as WC on CPU side. Since such allocations are not all done through GuC allocator, to avoid too many code changes, the i915_coherent_map_type() is now hard coded to return WC for MTL. v2: Simplify the commit message(Matt). BSpec: 45101 Signed-off-by: Fei Yang <fei.yang@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230424182902.3663500-3-fei.yang@intel.com
2023-04-25drm/i915/mtl: Add PTE encode functionFei Yang
PTE encode functions are platform dependent. This patch implements PTE functions for MTL, and ensures the correct PTE encode function is used by calling pte_encode function pointer instead of the hardcoded gen8 version of PTE encode. Fixes: b76c0deef627 ("drm/i915/mtl: Define MOCS and PAT tables for MTL") Signed-off-by: Fei Yang <fei.yang@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Nirmoy Das <nirmoy.das@intel.com> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230424182902.3663500-2-fei.yang@intel.com
2023-04-24drm/amdgpu/gfx11: update gpu_clock_counter logicAlex Deucher
This code was written prior to previous updates to this logic for other chips. The RSC registers are part of SMUIO which is an always on block so there is no need to disable gfxoff. Additionally add the carryover and preemption checks. v2: rebase Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amdgpu: support psp vbflash sysfs for MP0 13_0_10Likun Gao
Add support for PSP vbflash sysfs interface with MP0 version v13.0.10. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24Revert "drm/amd/display: disable SubVP + DRR to prevent underflow"Aurabindo Pillai
This reverts commit 80c6d6804f31451848a3956a70c2bcb1f07cfcb0. The orignal commit was intended as a workaround to prevent underflow and flickering when using one normal monitor and the other high refresh rate monitor (> 120Hz). This patch is being reverted in favour of a software solution to enable SubVP+DRR Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: 3.2.233Aric Cyr
This DC version brings along: - Improvements in the SubVP feature - Keep disable aux-i delay as 0 - Add p-state debugging and improvements - Fix in secure display context creation - add option to use custom backlight caps - Lowering min Z8 residency time - Restore rptr/wptr for DMCUB as workaround - Update FW feature caps struct Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Keep disable aux-i delay as 0Michael Strauss
[WHY] Current Aux-I sequence checks for local_sink which isn't populated on MST links [HOW] Leave disable aux-i delay as 0 for MST cases Cc: stable@vger.kernel.org Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Query GECC enable for SubVP disableAlvin Lee
- We want to disable SubVP if Graphics Error Correction/Correcting Code (GECC) is enabled. - After reading feature caps from DMCUB during init, use the GECC enable/disable info to determine if SubVP can be enabled or not. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Enable SubVP for high refresh rate displaysAlvin Lee
[Description] - Add debug option to enable SubVP for high refresh rate displays - For now limit the enabled modes based on a table in debug options - Currently disabled by default Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: For no plane case set pstate support in validationAlvin Lee
- Previously update_clocks was overriding pstate support if it checked that there were no planes - However, P-State support should be determined in validation phase instead - This fixes an issue where a transition from FPO -> no planes expects UCLK MAX, but update_clocks was overriding to set UCLK to min Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Add p-state debuggingSung Lee
[WHY] P-State related issues are fairly common but currently there is no way to debug these issues after the fact. [HOW] Add helpful registers to HW state queries Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Sung Lee <sunglee@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: update extended blank for dcn314 onwardsGabe Teeger
[Why] Flickering and underflow was observed when testing extended blank on dcn314. [What] Vstartup is contrainted by vblank_nom, so adjusting it to include non-adjusted vtotal in its calculation during freesync video means that Vstartup is not changed when vtotal changes. This fixed the flickering + underflow. dc_extended_blank_supported function was removed because extended blank is only relevant to when zstate is supported. The increased vtotal during freesync can be passed to dml regardless of whether extended blank is supported or not, so this function is not needed. Updates were made recently in dml to the calculation of min_dst_y_next_start. Dml input for dcn314 will now always use the newer calculation for min_dst_y_next_start. Dml input for older dcn versions remains untouched. The variable optimized_min_dst_y_next_start is replaced everywhere with min_dst_y_next_start, and the updated dml allows min_dst_y_next_start to increase to an optimized value during freesync video, then return to default when freesync is disengaged. Also removed registry key for controlling extended blank feature. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Fix in secure display context creationAlan Liu
[Why & How] We need to store CRTC information in secure_display_ctx, so postpone the call to amdgpu_dm_crtc_secure_display_create_contexts() until we initialize all CRTCs. Cc: stable@vger.kernel.org Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Update scaler recout data for visual confirmLeo (Hanghong) Ma
[Why] Our QA found visual confirm color is not as expected for Auto Color Management feature test after enable it. [How] Calculate scaler recout data when visual confirm enabled to update the visual confirm bar on the display. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Program OTG vtotal min/max selectors unconditionallyAurabindo Pillai
OTG_V_TOTAL_MIN/MAX_SEL bits are required to be programmed to 1 if writes to OTG timing registers need to be honoured. This is usually needed only when freesync is active. However, SubVP + DRR requires that we're able to change timing even without freesync being active (but supported). By unconditionally writing this bit to 1, we remove an unnecessary dependency so that DMCUB can change OTG timing whenever it wants. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: add option to use custom backlight capsJosip Pavic
[Why & How] Provide option for vendors to specify a custom brightness-to-backlight conversion profile. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Lowering min Z8 residency timeLeo Chen
[Why & How] Per HW team request, we're lowering the minimum Z8 residency time to 2000us. This enables Z8 support for additional modes we were previously blocking like 2k>60hz Cc: stable@vger.kernel.org Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Enable SubVP on PSR panels if single streamAlvin Lee
Enable SubVP on PSR panels now that we have FW support Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: add pixel rate based CRB allocation supportDmytro Laktyushkin
This feature is meant to unblock PSTATE for certain high end display configs on dcn315. This is achieved by allocating CRB to detile buffer based on display requirements to meet pstate latency hiding needs. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Limit DCN32 8 channel or less parts to DPM1 for FPOAlvin Lee
- Due to hardware related QoS issues, we need to limit certain SKUs with less memory channels to DPM1 and above. - At DPM0 + workload running, the urgent return latency can exceed 15us (the expected maximum is 4us) which results in underflow Cc: stable@vger.kernel.org Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Restore rptr/wptr for DMCUB as workaroundJinZe.Xu
[Why] States may be desync after resume. [How] Sync sw state with hw state. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: Update FW feature caps structAlvin Lee
Reorder FW feature caps struct variable order to ensure backwards compatability is maintained for older FW Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Sung Lee <Sung.Lee@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: implement force function in amdgpu_dm_connector_funcsAlex Hung
[Why] When userspace (IGT) inserts EDID with audio data (ELD), EDID is not updated. [How] Implements force function (amdgpu_dm_connector_funcs_force) in amdgpu_dm_connector_funcs to create emulated sink and to handle EDID. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenchieh Chien <wenchieh.chien@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: 3.2.232Aric Cyr
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amd/display: [FW Promotion] Release 0.0.163.0Anthony Koo
Add feature caps for Subvp + PSR so driver is back compatible Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amdgpu: add debugfs interface for reading MQDsAlex Deucher
Provide a debugfs interface to access the MQD. Useful for debugging issues with the CP and MES hardware scheduler. v2: fix missing unreserve/unmap when pos >= size (Alex) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-24drm/amdgpu: track MQD size for gfx and computeAlex Deucher
It varies by generation and we need to know the size to expose this via debugfs. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-21 08:17:59 +0000