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path: root/drivers/gpu
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2024-05-13drm/amdgpu: remove structurally dead codeJesse Zhang
This code cannot be reached: return "UNKNOWN";. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: fix enum feature compared against 0Jesse Zhang
This less-than-zero comparison of an unsigned value is never true. feature < 0U Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: fix enum type compared against 0Jesse Zhang
This less-than-zero comparison of an unsigned value is never true. type < 0U Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgu: remove unused codeJesse Zhang
The same code is executed when the condition err is true or false, because the code in the if-then branch and after the if statement is identical Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: remove logically dead code for renoirJesse Zhang
The switch governing value clk_type cannot be SMU_GFXCLK and SMU_SCLK. Fixes: ca55f459f5ad ("drm/amd/pm: add the fine grain tuning function for Renoir") Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu: remove structurally dead code for amd_gmcJesse Zhang
This code cannot be reached: return sysfs_emit(buf, "UNK....) Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: check the return of send smc msg for smu_v13Jesse Zhang
Set smu work laod mask may fail, so check return. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: check specific index for smu13Jesse Zhang
Check for specific indexes that may be invalid values. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by: Tim Huang <Tim.Huang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: check the return of send smc msg for navi10Jesse Zhang
Set smu work laod mask may fail, so check return. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: check the return of send smc msg for sienna_cichildJesse Zhang
Set smu work laod mask may fail, so check return. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: check specific index for aldebaranJesse Zhang
Check for specific indexes that may be invalid values. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd: fix the warning unchecking return vaule for sdma_v7Jesse Zhang
check ring allocate success before emit preempt ib Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu: clear the warning unsigned compared against 0 for xcp_idJesse Zhang
This greater-than-or-equal-to-zero comparison of an unsigned value is always true. fpriv->xcp_id >= 0U Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu: fix the waring dereferencing hiveJesse Zhang
Check the amdgpu_hive_info *hive that maybe is NULL. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu: fix dereference after null checkJesse Zhang
check the pointer hive before use. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: fix get dpm level count for yello carpJesse Zhang
For invalid clk types, return -EINVAL to check the return. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu/pm: Drop redundant setting code for pcie lanesMa Jun
Drop redundant setting code for pcie.lanes. It overwrites the value get from pptable Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Acked-by: Yang Wang<kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu/pm: Fix code alignment issueMa Jun
Fix code alignment issue Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Reported-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: fix get dpm level count for smu13Jesse Zhang
For invalid clk types, return -EINVAL to check the return. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu: Fix the warning division or modulo by zeroJesse Zhang
Checks the partition mode and returns an error for an invalid mode. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13Revert "drm/amd/display: Enable SYMCLK gating in DCCG"Alex Hung
This reverts commit c49e44ede5cdfe650c2f769d8bd58cbe289e87cd. This causes regression on DP link layer test. Reported-by: Mark Broadworth <Mark.Broadworth@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdkfd: Fix CU Masking for GFX 9.4.3Mukul Joshi
We are incorrectly passing the first XCC's MQD when updating CU masks for other XCCs in the partition. Fix this by passing the MQD for the XCC currently being updated with CU mask to update_cu_mask function. Fixes: fc6efed2c728 ("drm/amdkfd: Update CU masking for GFX 9.4.3") Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: 3.2.285Aric Cyr
This version brings along following fixes: - Read default boot options - Find max flickerless instant vtotal delta - Refactor dcn401_update_clocks - Reduce I2C speed to 95kHz in DCN401 - Allow higher DSC slice support for small timings on dcn401 - Don't offload flip if not only address update - Check UHBR13.5 cap when determining max link cap - Enable SYMCLK gating in DCCG - Expand to higher link rates - Add left edge pixel for YCbCr422/420 + ODM pipe split - Add resource interfaces for get ODM slice rect - Add COEF filter types for DCN401 - Refactor DCN401 DCCG into component directory - Fix 3dlut size for Fastloading on DCN401 - Fix write to non-existent reg on DCN401 - Remove USBC check for DCN32 - Remove unused code for some dc files - Disable AC/DC codepath when unnecessary - Create dcn401_clk_mgr struct Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Read default boot optionsDuncan Ma
[WHY] DPIA boot option is set by VBIOS. It gets overwritten when driver loads DMU. [HOW] Read PreOS boot options and determine if dpia is enabled. Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Find max flickerless instant vtotal deltaEthan Bitnun
[WHAT & HOW] - Populate dml 2 callback with get_max_flickerless_instant_vtotal_increase - Use long long when necessary to prevent overflow - Add asic specific default values, currently disabled by default for every asic - Use the pre-existing debug option to protect the call to get_max_flickerless_instant_vtotal_increase Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ethan Bitnun <etbitnun@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Refactor dcn401_update_clocksDillon Varone
[WHY & HOW] Refactor complex code into manageable functions. This also cleans up some updating logics. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Reduce I2C speed to 95kHz in DCN401Chris Park
[WHY] HW for DCN401 is presented with a small I2C speed fluctuation that exceeds the hard cap limitation of 100kHz occasionally. This violates compliance requirement and will result in failure in compliance. [HOW] After various measurements and traceback to previous generation HW, DCN IP, SI and SW driver agrees that we can reduce I2C speed to 95kHz to address the I2C spped fluctuation in DCN401. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Allow higher DSC slice support for small timings on dcn401Wenjing Liu
[WHY] DML2.1 has added the support to determine ODM combine based on DSC slice count limitation. This support would allow us to support DSC slice higher than 4 on small timings. The change will allow higher DSC slice support independent from pixel clock in use. [HOW] Add a DCN401 get_enc_caps function to allow the support for DSC slice count higher than 4. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Don't offload flip if not only address updateAlvin Lee
[WHAT & HOW] Fast updates can consist of some stream updates as well (i.e., out_csc). In these cases we should not offload the flip to FW as we can only offload address only updates to FW. Reviewed-by: Chris Park <chris.park@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Check UHBR13.5 cap when determining max link capGeorge Shen
[WHY] UHBR13.5 support is optional, even if UHBR20 is supported by the device. If source supports max UHBR13.5 while sink, cable and LTTPR support UHBR20 but not UHBR13.5, UHBR10 should be used as the max link cap. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Enable SYMCLK gating in DCCGDaniel Miess
[WHY & HOW] Enable root clock optimization for SYMCLK and only disable it when it's actively used. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Daniel Miess <daniel.miess@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Expand to higher link ratesSung Joon Kim
[WHY & HOW] To support higher link rates that sink allows, we need to make sure driver is ready and perform correct link-training sequence. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe splitWenjing Liu
[WHY] Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM pipesplit is used, pixels on the left edge of ODM slices need one extra pixel from the right edge of the previous slice to calculate the correct chroma value. Without this change, the chroma value is slightly different than expected. This is usually imperceptible visually, but it impacts test pattern CRCs for compliance test automation. [HOW] Update logic to use the register for adding extra left edge pixel for YCbCr422/420 ODM cases. Reviewed-by: George Shen <george.shen@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Add resource interfaces for get ODM slice rectWenjing Liu
[WHY] We need an unified location to perform ODM slice rect calculation. [HOW] Add three interfaces for ODM slice rect/width calucaltion in resource.h Reviewed-by: George Shen <george.shen@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Add COEF filter types for DCN401Samson Tam
Add VERTICAL_BLUR_SCALE & HORIZONTAL_BLUR_SCALE types. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Refactor DCN401 DCCG into component directoryRevalla Hari Krishna
[WHY] Clean up the code that requires dccg to be in its own component. [HOW] Move all files under newly created dccg dir and fix the makefiles. Acked-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Revalla Hari Krishna <Harikrishna.Revalla@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Fix 3dlut size for Fastloading on DCN401Adam Nelson
[WHY] After a non-3dlut test the MPCC_MCM_3DLUT_MODE::MPCC_MCM_3DLUT_SIZE is incorrect. [HOW] Add register write to make valid. Acked-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Adam Nelson <adnelson@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Fix write to non-existent reg on DCN401Ilya Bakoulin
DP_DSC_CNTL no longer exists on DCN401. Acked-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Remove USBC check for DCN32Rodrigo Siqueira
The CONNECTOR_ID_USBC check was removed to fix a regression, but it was re-introduced by accident. This commit drops the USBC that causes the regressions. Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Remove unused code for some dc filesRodrigo Siqueira
Cleanup unused code in DC. Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Disable AC/DC codepath when unnecessaryJoshua Aberback
[WHY] If there are no DC clock limits present, or if the DC limits are the same as the AC limits, we can disable the AC/DC codepath as there won't be any validation differences between the two modes. [HOW] When all DC power mode clock limits are the same as the max clock values, there won't be any difference between AC mode and DC mode. Zero out DC limits that equal max and provide a new cap to indicate the presence of any non-zero DC mode limit. In summary: - zero out DC limits that are the same as max clock value - new dc cap to indicate the presence of DC mode limits - set limits present if any clock has distinct AC and DC values from SMU Acked-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/display: Create dcn401_clk_mgr structDillon Varone
Create dcn401 specific structure to encapsulate version specific variables. Acked-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu/umsch: add support to capture fw debug logSaleemkhan Jamadar
Added support to capture unsch fw debug logs in debugfs. To enable set amdgpu_umschfw_log =1 in boot args. v1 - rename variable to umsch_mm_fwlog (Veera) Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/amdgpu: update jpeg 5 capabilityDavid (Ming Qiang) Wu
Based on the documentation the maximum resolustion should be 16384x16384. Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu/vcn: set VCN5 power gating state to GATE on suspendDavid (Ming Qiang) Wu
On suspend, we need to set power gating state to GATE when VCN5 is busy, otherwise we will get following error on resume: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring vcn_unified_0 test failed (-110) [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <vcn_v5_0_0> failed -110 amdgpu: amdgpu_device_ip_resume failed (-110). PM: dpm_run_callback(): pci_pm_resume+0x0/0x100 returns -110 PM: failed to resume async: error -110 Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu/vcn: remove irq disabling in vcn 5 suspendDavid (Ming Qiang) Wu
We do not directly enable/disable VCN IRQ in vcn 5.0.0. And we do not handle the IRQ state as well. So the calls to disable IRQ and set state are removed. This effectively gets rid of the warining of "WARN_ON(!amdgpu_irq_enabled(adev, src, type))" in amdgpu_irq_put(). Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu/pm: Check input value for power profile setting on smu11, smu13 ↵Ma Jun
and smu14 Check the input value for CUSTOM profile mode setting on smu 11, smu13 and smu14. Otherwise we use uninitialized value of input[] Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amdgpu/pm: Check input value for CUSTOM profile mode setting on legacy SOCsMa Jun
Check the input value for CUSTOM profile mode setting on legacy SOCs. Otherwise we may use uninitalized value of input[] Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/amd/pm: remove deprecated I2C_CLASS_SPD support from newly added SMU_14_0_2Heiner Kallweit
Support for I2C_CLASS_SPD is currently being removed from the kernel. Only remaining step is to remove the definition of I2C_CLASS_SPD. Setting I2C_CLASS_SPD in a driver is a no-op meanwhile, so remove it here. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-13drm/radeon: Delay Connector detecting when HPD singals is unstableShixiong Ou
In some causes, HPD signals will jitter when plugging in or unplugging HDMI. Rescheduling the hotplug work for a second when EDID may still be readable but HDP is disconnected, and fixes this issue. Signed-off-by: Shixiong Ou <oushixiong@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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