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2024-05-30drm: atmel-hlcdc: add LCD controller layer definition for sam9x75Manikandan Muralidharan
Add the LCD controller layer definition and descriptor structure for sam9x75 for the following layers: - Base Layer - Overlay1 Layer - Overlay2 Layer - High End Overlay Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-9-manikandan.m@microchip.com
2024-05-30drm: atmel-hlcdc: add support for DSI output formatsManikandan Muralidharan
Add support for the following DPI mode if the encoder type is DSI as per the XLCDC IP datasheet: - 16BPPCFG1 - 16BPPCFG2 - 16BPPCFG3 - 18BPPCFG1 - 18BPPCFG2 - 24BPP Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> [durai.manickamkr@microchip.com: update output format using is_xlcdc flag] Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-8-manikandan.m@microchip.com
2024-05-30drm: atmel-hlcdc: add vertical and horizontal scaling support for XLCDCManikandan Muralidharan
Update the vertical and horizontal scaler registers of XLCDC IP with Bilinear and Bicubic co-efficients taps for Chroma and Luma componenets of the Pixel. Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-7-manikandan.m@microchip.com
2024-05-30drm: atmel-hlcdc: add DPI mode support for XLCDCManikandan Muralidharan
Add support for Display Pixel Interface (DPI) Compatible Mode support in atmel-hlcdc driver for XLCDC IP along with legacy pixel mapping. DPI mode BIT is configured in LCDC_CFG5 register. Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> [durai.manickamkr@microchip.com: update DPI mode bit using is_xlcdc flag] Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-6-manikandan.m@microchip.com
2024-05-30drm: atmel_hlcdc: Add support for XLCDC using IP specific driver opsManikandan Muralidharan
Add XLCDC specific driver ops and is_xlcdc flag to separate the functionality and to access the controller registers. HEO scaling, window resampling, Alpha blending, YUV-to-RGB conversion in XLCDC is derived and handled using additional configuration bits and registers. Writing one to the Enable fields of each layer in LCD_ATTRE is required to reflect the values set in Configuration, FBA, Enable registers of each layer. Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Co-developed-by: Hari Prasath Gujulan Elango <Hari.PrasathGE@microchip.com> Signed-off-by: Hari Prasath Gujulan Elango <Hari.PrasathGE@microchip.com> Co-developed-by: Durai Manickam KR <durai.manickamkr@microchip.com> Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-5-manikandan.m@microchip.com
2024-05-30drm: atmel_hlcdc: replace regmap_read with regmap_read_poll_timeoutManikandan Muralidharan
Replace regmap_read with regmap_read_poll_timeout to neatly handle retries Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Acked-by: Dharma Balasubiramani <dharma.b@microchip.com> Reviewed-by: Hari Prasath Gujulan Elango <hari.prasathge@microchip.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-4-manikandan.m@microchip.com
2024-05-30drm: atmel-hlcdc: Define XLCDC specific registersDurai Manickam KR
The register address of the XLCDC IP used in SAM9X7 SoC family are different from the previous HLCDC. Defining those address space with valid macros. Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com> [manikandan.m@microchip.com: Remove unused macro definitions] Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-3-manikandan.m@microchip.com
2024-05-30drm: atmel-hlcdc: add driver ops to differentiate HLCDC and XLCDC IPManikandan Muralidharan
Add LCD IP specific ops in driver data to differentiate HLCDC and XLCDC code within the atmel-hlcdc driver files. XLCDC in SAM9X7 has different sets of registers and additional configuration bits when compared to previous HLCDC IP. Read/write operation on the controller register and functionality is now separated using the LCD IP specific ops. Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-2-manikandan.m@microchip.com
2024-05-30drm/panel: sitronix-st7789v: fix display size for jt240mhqs_hwt_ek_e3 panelGerald Loacker
This is a portrait mode display. Change the dimensions accordingly. Fixes: 0fbbe96bfa08 ("drm/panel: sitronix-st7789v: add jasonic jt240mhqs-hwt-ek-e3 support") Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net> Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com> Link: https://lore.kernel.org/r/20240409-bugfix-jt240mhqs_hwt_ek_e3-timing-v2-3-e4821802443d@wolfvision.net Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240409-bugfix-jt240mhqs_hwt_ek_e3-timing-v2-3-e4821802443d@wolfvision.net
2024-05-30drm/panel: sitronix-st7789v: tweak timing for jt240mhqs_hwt_ek_e3 panelGerald Loacker
Use the default timing parameters to get a refresh rate of about 60 Hz for a clock of 6 MHz. Fixes: 0fbbe96bfa08 ("drm/panel: sitronix-st7789v: add jasonic jt240mhqs-hwt-ek-e3 support") Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net> Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com> Link: https://lore.kernel.org/r/20240409-bugfix-jt240mhqs_hwt_ek_e3-timing-v2-2-e4821802443d@wolfvision.net Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240409-bugfix-jt240mhqs_hwt_ek_e3-timing-v2-2-e4821802443d@wolfvision.net
2024-05-30drm/panel: sitronix-st7789v: fix timing for jt240mhqs_hwt_ek_e3 panelGerald Loacker
Flickering was observed when using partial mode. Moving the vsync to the same position as used by the default sitronix-st7789v timing resolves this issue. Fixes: 0fbbe96bfa08 ("drm/panel: sitronix-st7789v: add jasonic jt240mhqs-hwt-ek-e3 support") Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net> Link: https://lore.kernel.org/r/20240409-bugfix-jt240mhqs_hwt_ek_e3-timing-v2-1-e4821802443d@wolfvision.net Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240409-bugfix-jt240mhqs_hwt_ek_e3-timing-v2-1-e4821802443d@wolfvision.net
2024-05-30drm/i915: move uapi.event outside spinlock in intel_crtc_vblank_workLuca Coelho
In intel_crtc_vblank_work(), we access uapi.event before grabbing the event_lock spinlock, but modify it inside the spinlock block. This causes some static analyzers to get confused and issue a warning. The uapi.event value is not protected by the event_lock, so we can safely move it out of the protected block to prevent false positives. Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528112901.476068-3-luciano.coelho@intel.com
2024-05-30drm/i915/bios: double check array-boundary in parse_sdvo_lvds_dataLuca Coelho
During static analysis, a concern was raised that we may access the dtd->dtd[] array out of bounds, because we are not checking whether the index we use is larger than the array. This should not be a problem as is, because the enumeration that is used for this index comes from "panel_type", which uses an enumeration with 4 items. But if this enumeration is ever changed, it can lead to hard-to-detect bugs, so better double-check it before using it as an index to the array. Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528112901.476068-2-luciano.coelho@intel.com
2024-05-30drm/i915/display: Add compare config for MTL+ platformsMika Kahola
Currently, we may bump into pll mismatch errors during the state verification stage. This happens when we try to use fastset instead of full modeset. Hence, we would need to add a check for pipe configuration to ensure that the sw and the hw configuration will match. In case of hw and sw mismatch, we would need to disable fastset and use full modeset instead. v2: Fix C10 error on PLL comparison (BAT) Use memcmp instead of fixed loops for pll config comparison (Jani) Clean up and use intel_cx0pll_dump_hw_state() to dump pll information (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240523134649.31452-3-mika.kahola@intel.com
2024-05-30drm/i915/display: Revert "drm/i915/display: Skip C10 state verification in ↵Mika Kahola
case of fastset" This reverts commit a1d91c6e989d0e66b89aa911f2cd459d7bdebbe5. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240523134649.31452-2-mika.kahola@intel.com
2024-05-29drm/xe: Decouple xe_exec_queue and xe_lrcNiranjana Vishwanathapura
Decouple xe_lrc from xe_exec_queue and reference count xe_lrc. Removing hard coupling between xe_exec_queue and xe_lrc allows flexible design where the user interface xe_exec_queue can be destroyed independent of the hardware/firmware interface xe_lrc. v2: Fix lrc indexing in wq_item_append() Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240530032211.29299-1-niranjana.vishwanathapura@intel.com
2024-05-29drm/xe: Remove unwanted mutex lockingNiranjana Vishwanathapura
Do not hold xef->exec_queue.lock mutex while parsing the xarray xef->exec_queue.xa in xe_file_close() as it is not needed and will cause an unwanted dependency between this lock and the vm->lock. This lock protects the exec queue lookup and reference taking which doesn't apply to this code path. When FD is closing, IOCTLs presumably can't be modifying the xarray. v2: Update commit text (Matt Brost) v3: Add more code comment (Rodrigo Vivi) v4: Further expand code comment (Rodirgo Vivi) Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Jagmeet Randhawa <jagmeet.randhawa@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529221639.23117-1-niranjana.vishwanathapura@intel.com
2024-05-29drm/amd/pm: remove deprecated I2C_CLASS_SPD support from newly added SMU_14_0_2Heiner Kallweit
Support for I2C_CLASS_SPD is currently being removed from the kernel. Only remaining step is to remove the definition of I2C_CLASS_SPD. Setting I2C_CLASS_SPD in a driver is a no-op meanwhile, so remove it here. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdgpu: Make CPX mode auto default in NPS4Rajneesh Bhardwaj
On GFXIP9.4.3, make CPX mode as the default compute mode if the node is setup in NPS4 memory partition mode. This change is only applicable for dGPU, for APU, continue to use TPX mode. Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdkfd: simplify APU VRAM handlingAlex Deucher
With commit 89773b85599a ("drm/amdkfd: Let VRAM allocations go to GTT domain on small APUs") big and small APU "VRAM" handling in KFD was unified. Since AMD_IS_APU is set for both big and small APUs, we can simplify the checks in the code. v2: clean up a few more places (Lang) Acked-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29Revert "drm/amdkfd: fix gfx_target_version for certain 11.0.3 devices"Alex Deucher
This reverts commit 28ebbb4981cb1fad12e0b1227dbecc88810b1ee8. Revert this commit as apparently the LLVM code to take advantage of this never landed. Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Feifei Xu <feifei.xu@amd.com>
2024-05-29drm/amdgpu: fix dereference null return value for the function ↵Jesse Zhang
amdgpu_vm_pt_parent The pointer parent may be NULLed by the function amdgpu_vm_pt_parent. To make the code more robust, check the pointer parent. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdgpu: silence UBSAN warningAlex Deucher
Convert a variable sized array from [1] to []. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdgpu: Adjust logic in amdgpu_device_partner_bandwidth()Alex Deucher
Use current speed/width on devices which don't support dynamic PCIe switching. Fixes: 466a7d115326 ("drm/amd: Use the first non-dGPU PCI device for BW limits") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3289 Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Move 'struct scaler_data' off stackArnd Bergmann
The scaler_data structure is implicitly copied onto the stack twice by being returned from a function. This is usually a bad idea, but it was not flagged by the compiler until a recent addition that pushed it over the 1024 byte function stack limit: drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_translation_helper.c: In function 'populate_dml_plane_cfg_from_plane_state': drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_translation_helper.c:1075:1: error: the frame size of 1032 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] Use an explicit kzalloc() and memcpy() instead here to keep it off the stack. Fixes: 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") Fixes: 7966f319c66d ("drm/amd/display: Introduce DML2") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: avoid large on-stack structuresArnd Bergmann
Putting excessively large objects on a function stack causes a warning about possibly overflowing the 8KiB of kernel stack: drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn401/dcn401_resource.c: In function 'dcn401_update_bw_bounding_box': drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn401/dcn401_resource.c:1599:1: error: the frame size of 1196 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] 1599 | } | ^ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c: In function 'dc_state_create': drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c:221:1: error: the frame size of 1196 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] 221 | } | ^ Use dynamic allocation instead. Fixes: e779f4587f61 ("drm/amd/display: Add handling for DC power mode") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: fix graphics_object_id sizeArnd Bergmann
The graphics_object_id structure is meant to fit into 32 bits, as it's passed by value in and out of functions. A recent change increased the size to 128 bits, so it's now always passed by reference, which is clearly not intended and ends up producing a compile-time warning: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c: In function 'construct_phy': drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:743:1: error: the frame size of 1040 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] Add back the bitfields to revert to the original size, while keeping the 'enum' type change. Fixes: fec85f995a4b ("drm/amd/display: Fix compiler redefinition warnings for certain configs") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: dynamically allocate dml2_configuration_options structuresArnd Bergmann
This structure is too large to fit on a stack, as shown by the newly introduced warnings from a recent code change: drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn32/dcn32_resource.c: In function 'dcn32_update_bw_bounding_box': drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn32/dcn32_resource.c:2019:1: error: the frame size of 1180 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn321/dcn321_resource.c: In function 'dcn321_update_bw_bounding_box': drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn321/dcn321_resource.c:1597:1: error: the frame size of 1180 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c: In function 'dc_state_create': drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c:219:1: error: the frame size of 1184 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] Instead of open-coding the assignment of a large structure to a stack variable, use an explicit kmemdup() in each case to move it off the stack. Fixes: e779f4587f61 ("drm/amd/display: Add handling for DC power mode") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drivers/gpu: Fix misalignment in comment blockBruno Rocha Levi
This patch fixes a warning from checkpatch by ensuring the trailing */ is aligned with the rest of the *, improving readability. Co-developed-by: Lucas Antonio <lucasantonio.santos@usp.br> Signed-off-by: Lucas Antonio <lucasantonio.santos@usp.br> Signed-off-by: Bruno Rocha Levi <brunolevilevi@usp.br> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdkfd: Replace deprecated gfx12 trap handler instructionsJay Cornwall
Newer assemblers reject S_WAITCNT. All instances of S_WAITCNT can be replaced by S_WAITCNT 0 (< gfx12) or S_WAIT_IDLE (>= gfx12) since there is no concurrency of different memory instruction classes. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdkfd: Sync trap handler binary with sourceJay Cornwall
Source and binary have become mismatched during branch activity. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd: Fix shutdown (again) on some SMU v13.0.4/11 platformsMario Limonciello
commit cd94d1b182d2 ("dm/amd/pm: Fix problems with reboot/shutdown for some SMU 13.0.4/13.0.11 users") attempted to fix shutdown issues that were reported since commit 31729e8c21ec ("drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11") but caused issues for some people. Adjust the workaround flow to properly only apply in the S4 case: -> For shutdown go through SMU_MSG_PrepareMp1ForUnload -> For S4 go through SMU_MSG_GfxDeviceDriverReset and SMU_MSG_PrepareMp1ForUnload Reported-and-tested-by: lectrode <electrodexsnet@gmail.com> Closes: https://github.com/void-linux/void-packages/issues/50417 Cc: stable@vger.kernel.org Fixes: cd94d1b182d2 ("dm/amd/pm: Fix problems with reboot/shutdown for some SMU 13.0.4/13.0.11 users") Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdgpu/gfx11: enable gfx pipe1 hardware supportAlex Deucher
Enable gfx pipe1 hardware support. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdgpu: Make CPX mode auto default in NPS4Rajneesh Bhardwaj
On GFXIP9.4.3, make CPX mode as the default compute mode if the node is setup in NPS4 memory partition mode. This change is only applicable for dGPU, for APU, continue to use TPX mode. Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdgpu/gfx11: handle priority setup for gfx pipe1Alex Deucher
Set up pipe1 as a high priority queue. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipeAlex Deucher
Use correct ref/mask for differnent gfx ring pipe. Ported from ZhenGuo's patch for gfx10. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdgpu: Add lock around VF RLCG interfaceVictor Skvortsov
flush_gpu_tlb may be called from another thread while device_gpu_recover is running. Both of these threads access registers through the VF RLCG interface during VF Full Access. Add a lock around this interface to prevent race conditions between these threads. Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amdkfd: simplify APU VRAM handlingAlex Deucher
With commit 89773b85599a ("drm/amdkfd: Let VRAM allocations go to GTT domain on small APUs") big and small APU "VRAM" handling in KFD was unified. Since AMD_IS_APU is set for both big and small APUs, we can simplify the checks in the code. v2: clean up a few more places (Lang) Acked-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29Revert "drm/amdkfd: fix gfx_target_version for certain 11.0.3 devices"Alex Deucher
This reverts commit 28ebbb4981cb1fad12e0b1227dbecc88810b1ee8. Revert this commit as apparently the LLVM code to take advantage of this never landed. Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Feifei Xu <feifei.xu@amd.com>
2024-05-29drm/amd/display: Enable copying of bounding box data from VBIOS DMUBAurabindo Pillai
Allocate some memory, send the address in chunks to dmub, and finally ask it to copy the bounding box data into the newly allocated memory. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Add new GPINT command definitionsAurabindo Pillai
New commands for enabling copy of DC bounding box values from VBIOS DMUB Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Move some init routines to dm_sw_init()Aurabindo Pillai
Move creation of CGS device node and the DAL allocation list from amdgpu_dm_init() to dm_sw_init() which runs before dmub's sw init hook. This is required for communicating with the VBIOS DMUB image from the VBIOS that was loaded for early pre-os boot. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Add missing registers for DCN401Rodrigo Siqueira
Add some additional registers. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Fix null pointer dereference for dcn401Aurabindo Pillai
When ODM slice happens on DCN401, there is a null pointer exception caused by that. This commit address this issue by checking if the required data structures are initialized. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Remove incorrect FP context startAurabindo Pillai
All the DC_FP_START/END should be used before call anything from DML2, for this reason, the use of those guards inside DML it is not correct. This commit removes two unnecessary DC_FP_START/END from a dml2 function. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Use DCN 410 includes for DCN401Aurabindo Pillai
DCN401 is using DCN 320 headers, which does not have all the right registers for DCN401. This commit just replace DCN320 includes with the one from DCN410. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Remove unnecessary HPD entry for DCN401Aurabindo Pillai
Drop the extra HPD irq entry for DCN401. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Update DML2.1 generated codeRodrigo Siqueira
Most of the DML code is generated, and it is necessary to update some parts of it from time to time. This commit brings the latest generated code for DML 2.1. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Refactor HUBP into component folder.Pinninti
[why] cleaning up the code refactor requires hubp to be in its own component. [how] move all files under newly created hubp folder and fixing the makefiles. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Pinninti <bpinnint@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-29drm/amd/display: Remove unused codeRodrigo Siqueira
This commit removes some unused code with the required adjustments. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-24 18:06:27 +0000