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2024-07-01drm/amd/display: Add debug option for disabling SLDO optimizationsNicholas Kazlauskas
[Why] DM can hook this up to disable SLDO optimizations in firmware during DMCUB initialization for debug purposes. [How] Add the option and pass it through dmub_srv. Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: un-block 8k with single dimmPaul Hsieh
[Why] Driver doesn't validate multi-display with scaling when OS calls DDI. This behavior causes the validated result to be a mismatch between some automated test cases. To address this issue, some workaround was added that caused issues in 8k. [How] Since the origin issue had been root caused, revert the previous workaround and unblock 8k with a single dimm. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Add available bandwidth calculation for audioRyan Seto
[Why] Audio for 8K 240Hz monitor was not available when it should be [How] Added calculation based on stream state Co-developed-by: Ryan Seto <ryanseto@amd.com> Reviewed-by: George Shen <george.shen@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Ryan Seto <ryanseto@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Add refresh rate range checkTom Chung
[Why] We only enable the VRR while monitor usable refresh rate range is greater than 10 Hz. But we did not check the range in DRM_EDID_FEATURE_CONTINUOUS_FREQ case. [How] Add a refresh rate range check before set the freesync_capable flag in DRM_EDID_FEATURE_CONTINUOUS_FREQ case. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Cleanup dce_get_dp_ref_freq_khzDillon Varone
[WHY&HOW] Cleanup unnecessary code pathes as compile guards were added and removed overtime. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Check denominator crb_pipes before usedAlex Hung
[WHAT & HOW] A denominator cannot be 0, and is checked before used. This fixes 2 DIVIDE_BY_ZERO issues reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Check denominator pbn_div before usedAlex Hung
[WHAT & HOW] A denominator cannot be 0, and is checked before used. This fixes 1 DIVIDE_BY_ZERO issue reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Adjust cursor visibility between MPC slicesNevenko Stupar
[Why & How] When MPC enabled, need to adjust x and hot spot x position on one pipe when the cursor is between MPC slices i.e. when the cursor is moving from one MPC slice to next slice, while whole cursor size is not contained within one pipe, to make part of the cursor to be visible on the other pipe. Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Nevenko Stupar <nevenko.stupar@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Skip unnecessary abm disableSherry Wang
[Why] We try to disable abm immediately when it's being gradually disabled, which causes backlight ramping being paused in the middle [How] Don't disable abm immediately if abm has been or is being disabled through set_abm_level path Reviewed-by: Anthony Koo <anthony.koo@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Sherry Wang <yao.wang1@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Fix possible overflow in integer multiplicationAlex Hung
[WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned/siged long long (64 bits). This can be fixed by casting integer to unsigned/siged long long to force 64 bits results. This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Add ASIC cap to limit DCC surface widthGeorge Shen
[Why] Certain configurations of DCN401 require ODM4:1 to support DCC for 10K surfaces. DCC should be conservatively disabled in those cases. The issue is that current logic limits 10K surface DCC for all configurations of DCN401. [How] Add DC ASIC cap to indicate max surface width that can support DCC. Disable DCC if this ASIC cap is non-zero and surface width exceeds it. Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Revert Add workaround to restrict max frac urgent for DPM0Teeger
This reverts commit 871512e36f9c1c2cb4e62eb860ca0438800e4d63 due to multiple issues found. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Teeger <gateeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Choose HUBP unbounded request based on DML outputSung Joon Kim
[why] Previously, we decide on the unbounded request purely based on pipe_cnt which is a wrong variable to use to determine how many pipes are in "use". DML already accounts for number of pipes in use along with other various factors and is a more reliable method of determination. [how] Use UnboundedRequestEnabledThisState to decide on unbounbded_req_enabled. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Remove unnecessary error messageJoshua Aberback
[Why] This error message is unnecessary because returning when aconnector is uninitialized is the desired outcome during initialization. As well, there is no equivalent error message for read_dpcd. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Fix divide by zero in CURSOR_DST_X_OFFSET calculationGeorge Shen
[Why] Certain situations cause pipes to have a recout of 0, such as when the dst_rect lies completely outside of a given ODM slice. [How] Skip calculation that transforms cursor coordinates to viewport space. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Reset freesync config before update new stateTom Chung
[Why] Sometimes the new_crtc_state->vrr_infopacket did not sync up with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. [How] Reset the freesync config before get_freesync_config_for_crtc() to make sure we have the correct new_crtc_state for VRR. Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Add replay state entry to replay_stateAnthony Koo
- Add new Replay states 2A (initial Replay entry) and 4E (frame update) to check is there is new frame update before sending Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Anthony Koo <anthony.koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: use vmalloc for struct dc_stateAlex Deucher
This is a big structure so use vmalloc as malloc can fail when there is memory pressure. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3454 Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/xe/oa: Destroy the stream_lock mutexAshutosh Dixit
The mutex allocated in xe_oa_stream_init() was never previously destroyed. Do so now. Fixes: e936f885f1e9 ("drm/xe/oa/uapi: Expose OA stream fd") Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240628052125.1847989-1-ashutosh.dixit@intel.com
2024-07-01drm/xe/rtp: Fix out-of-bounds array accessLucas De Marchi
Increment the counter before checking for number of rules, otherwise when there's no XE_RTP_MATCH_OR an out-of-bounds access is done, as reported by kasan: BUG: KASAN: global-out-of-bounds in rule_matches+0xb6d/0x11c0 [xe] Read of size 1 at addr ffffffffa0a50b70 by task systemd-udevd/243 Fixes: dc72c52a42e0 ("drm/xe/rtp: Allow to OR rules") Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240628161726.836734-1-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2024-07-01drm/xe/pf: Restart VFs provisioning after GT resetMichal Wajdeczko
Any prior configurations pushed to the GuC are lost when the GT is reset. Push again all non-empty VF configurations to the GuC as part of the GuC reset procedure. This will also help restore early manual provisioning, when the PF was in the meantime suspended and then resumed. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240701102738.934-3-michal.wajdeczko@intel.com
2024-07-01drm/xe/pf: Skip fair VFs provisioning if already provisionedMichal Wajdeczko
Our debugfs allows to view and change VFs' provisioning configs. If we attempt to experiment with VFs provisioning before enabling them, this early config will affect fair provisioning calculations, and will also be overwritten, which is undesirable behavior. To improve this, check if the VFs configs are empty (unprovisioned) before starting the fair provisioning procedure. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240701102738.934-2-michal.wajdeczko@intel.com
2024-07-01drm/xe/pf: Remove inlined #ifdef CONFIG_PCI_IOVMichal Wajdeczko
We can remove #ifdef CONFIG_PCI_IOV in .c files if we provide dummy replacement of the xe_pci_sriov_configure() function. Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Francois Dugast <francois.dugast@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240627104305.1477-1-michal.wajdeczko@intel.com
2024-07-01drm/xe/guc: Configure TLB timeout based on CT buffer sizeNirmoy Das
GuC TLB invalidation depends on GuC to process the request from the CT queue and then the real time to invalidate TLB. Add a function to return overestimated possible time a TLB inval H2G might take which can be used as timeout value for TLB invalidation wait time. v4: Make sure CTB is in 4K blocks(Michal) and other doc fixes v3: Pass CT to xe_guc_ct_queue_proc_time_jiffies() (Michal) Add tlb_timeout_jiffies() that replaces TLB_TIMEOUT(Michal) v2: Address reviews from Michal. Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1622 Cc: Matthew Brost <matthew.brost@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Acked-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240628085845.2369-1-nirmoy.das@intel.com Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
2024-07-01drm/i915: Skip programming FIA link enable bits for MTL+Gustavo Sousa
Starting with Xe_LPD+, although FIA is still used to readout Type-C pin assignment, part of Type-C support is moved to PICA and programming PORT_TX_DFLEXDPMLE1(*) registers is not applicable anymore like it was for previous display IPs (e.g. see BSpec 49190). v2: - Mention Bspec 49190 as a reference of instructions for previous IPs. (Shekhar Chauhan) - s/Xe_LPDP/Xe_LPD+/ in the commit message. (Matt Roper) - Update commit message to be more accurate to the changes in the IP. (Imre Deak) Bspec: 65750, 65448 Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240625202652.315936-1-gustavo.sousa@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2024-07-01drm: panel-orientation-quirks: Add labels for both Valve Steam Deck revisionsMatthew Schwartz
This accounts for the existence of two Steam Deck revisions instead of a single revision Signed-off-by: Matthew Schwartz <mattschwartz@gwu.edu> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240628205822.348402-3-mattschwartz@gwu.edu
2024-07-01drm: panel-orientation-quirks: Add quirk for Valve GalileoJohn Schoenick
Valve's Steam Deck Galileo revision has a 800x1280 OLED panel Cc: stable@vger.kernel.org # 6.1+ Signed-off-by: John Schoenick <johns@valvesoftware.com> Signed-off-by: Matthew Schwartz <mattschwartz@gwu.edu> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240628205822.348402-2-mattschwartz@gwu.edu
2024-07-01drm/tests: Add tests for the new Monochrome value of tv_modeDave Stevenson
Adds test for the cmdline parser, connector property, and drm_analog_tv_mode to ensure the behaviour of the new value is correct. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240620110947.3615207-1-dave.stevenson@raspberrypi.com
2024-07-01drm/i915/display: For MTL+ platforms skip mg dp programmingImre Deak
For MTL+ platforms we use PICA chips for Type-C support and hence mg programming is not needed. Fixes issue with drm warn of TC port not being in legacy mode. Cc: stable@vger.kernel.org Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240625111840.597574-1-mika.kahola@intel.com (cherry picked from commit aaf9dc86bd806458f848c39057d59e5aa652a399) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-30drm/lima: Mark simple_ondemand governor as softdepDragan Simic
Lima DRM driver uses devfreq to perform DVFS, while using simple_ondemand devfreq governor by default. This causes driver initialization to fail on boot when simple_ondemand governor isn't built into the kernel statically, as a result of the missing module dependency and, consequently, the required governor module not being included in the initial ramdisk. Thus, let's mark simple_ondemand governor as a softdep for Lima, to have its kernel module included in the initial ramdisk. This is a rather longstanding issue that has forced distributions to build devfreq governors statically into their kernels, [1][2] or may have forced some users to introduce unnecessary workarounds. Having simple_ondemand marked as a softdep for Lima may not resolve this issue for all Linux distributions. In particular, it will remain unresolved for the distributions whose utilities for the initial ramdisk generation do not handle the available softdep information [3] properly yet. However, some Linux distributions already handle softdeps properly while generating their initial ramdisks, [4] and this is a prerequisite step in the right direction for the distributions that don't handle them properly yet. [1] https://gitlab.manjaro.org/manjaro-arm/packages/core/linux-pinephone/-/blob/6.7-megi/config?ref_type=heads#L5749 [2] https://gitlab.com/postmarketOS/pmaports/-/blob/7f64e287e7732c9eaa029653e73ca3d4ba1c8598/main/linux-postmarketos-allwinner/config-postmarketos-allwinner.aarch64#L4654 [3] https://git.kernel.org/pub/scm/utils/kernel/kmod/kmod.git/commit/?id=49d8e0b59052999de577ab732b719cfbeb89504d [4] https://github.com/archlinux/mkinitcpio/commit/97ac4d37aae084a050be512f6d8f4489054668ad Cc: Philip Muller <philm@manjaro.org> Cc: Oliver Smith <ollieparanoid@postmarketos.org> Cc: Daniel Smith <danct12@disroot.org> Cc: stable@vger.kernel.org Fixes: 1996970773a3 ("drm/lima: Add optional devfreq and cooling device support") Signed-off-by: Dragan Simic <dsimic@manjaro.org> Signed-off-by: Qiang Yu <yuq825@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/fdaf2e41bb6a0c5118ff9cc21f4f62583208d885.1718655070.git.dsimic@manjaro.org
2024-06-29drm/msm/adreno: Introduce gmu_chipid for a740 & a750Akhil P Oommen
To simplify, introduce the new gmu_chipid for a740 & a750 GPUs. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601396/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-06-29drm/msm/adreno: Add support for X185 GPUAkhil P Oommen
Add support in drm/msm driver for the Adreno X185 gpu found in Snapdragon X1 Elite chipset. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601399/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-06-29drm/msm/adreno: fix a743 and a740 cx mem initNeil Armstrong
Disable the call to qcom_scm_gpu_init_regs() for a730 and a740 after init failures on the HDK8550 and HDK8450 platforms: msm_dpu ae01000.display-controller: failed to load adreno gpu msm_dpu ae01000.display-controller: failed to bind 3d00000.gpu (ops a3xx_ops [msm]): -5 msm_dpu ae01000.display-controller: adev bind failed: -5 While debugging, it happens the call to: qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ) returns -5 and makes the gpu fail to initialize. Remove the scm call since it's not done downstream either and works fine without. Fixes: 14b27d5df3ea ("drm/msm/a7xx: Initialize a750 "software fuse"") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/600972/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-06-29drm/msm/adreno: fix a7xx gpu initNeil Armstrong
The gpulist has twice the a6xx gpulist, replace the second one with the a7xx gpulist. Solves: msm_dpu ae01000.display-controller: Unknown GPU revision: 7.3.0.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.10.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.20.1 on SM8450, SM8550 & SM8560. Fixes: 8ed322f632a9 ("drm/msm/adreno: Split up giant device table") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/600939/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-06-29Revert "drm/msm/a6xx: Poll for GBIF unhalt status in hw_init"Konrad Dybcio
Commit f6ebff4fe810 ("drm/msm/adreno: De-spaghettify the use of memory barriers") made some fixups relating to write arrival, ensuring that the GPU's memory interface has *really really really* been told to come out of reset. That in turn rendered the hacky commit being reverted no longer necessary. Get rid of it. This reverts commit b77532803d11 ("drm/msm/a6xx: Poll for GBIF unhalt status in hw_init") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/600870/ Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-06-29drm/msm/adreno: De-spaghettify the use of memory barriersKonrad Dybcio
Memory barriers help ensure instruction ordering, NOT time and order of actual write arrival at other observers (e.g. memory-mapped IP). On architectures employing weak memory ordering, the latter can be a giant pain point, and it has been as part of this driver. Moreover, the gpu_/gmu_ accessors already use non-relaxed versions of readl/writel, which include r/w (respectively) barriers. Replace the barriers with a readback (or drop altogether where possible) that ensures the previous writes have exited the write buffer (as the CPU must flush the write to the register it's trying to read back). Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/600869/ Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-06-28kernel-wide: fix spelling mistakes like "assocative" -> "associative"Jesse Brandeburg
There were several instances of the string "assocat" in the kernel, which should have been spelled "associat", with the various endings of -ive, -ed, -ion, and sometimes beginnging with dis-. Add to the spelling dictionary the corrections so that future instances will be caught by checkpatch, and fix the instances found. Originally noticed by accident with a 'git grep socat'. Link: https://lkml.kernel.org/r/20240612001247.356867-1-jesse.brandeburg@intel.com Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Cc: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2024-06-28drm/xe/mcr: Avoid clobbering DSS steeringMatt Roper
A couple copy/paste mistakes in the code that selects steering targets for OADDRM and INSTANCE0 unintentionally clobbered the steering target for DSS ranges in some cases. The OADDRM/INSTANCE0 values were also not assigned as intended, although that mistake wound up being harmless since the desired values for those specific ranges were '0' which the kzalloc of the GT structure should have already taken care of implicitly. Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240626210536.1620176-2-matthew.d.roper@intel.com
2024-06-28drm/xe/mocs: Clarify difference between hw and sw sizesMatt Roper
It's not very obvious what the difference is between the 'size' and 'n_entries' fields of the MOCS structure. Rename both fields slightly and add some comments explaining that one is the documentation-defined table size, while the other is the number of entries that can be programmed into the hardware (and the documented table size can potentially be smaller than the number of hardware entries). Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240627203741.2042752-4-matthew.d.roper@intel.com
2024-06-28drm/xe/mocs: Update MOCS assertions and remove redundant checksMatt Roper
Rely more heavily on assertions to describe the MOCS programming invariants. CI checks these assertions and will ensure no violations sneak in due to programmer error, so we can remove some of the redundant WARN and silent return checks from non-debug builds. Also tweak/augment some of the existing assertions: there's no reason we'd ever want a platform not to have a MOCS 'ops' structure hooked up so ensure info->ops is non-NULL. Likewise, we should never have a case where the bspec-defined MOCS setting table is larger than the number of MOCS registers exposed by the hardware, so add an extra assert on those sizes as well. Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240627203741.2042752-3-matthew.d.roper@intel.com
2024-06-28drm/xe: Get hwe domain specific FW to read RING_TIMESTAMPUmesh Nerlige Ramappa
Per client engine utilization uses RING_TIMESTAMP to return drm-total-cycles to the user. Current code uses XE_FW_GT to read this register on the first available engine in a GT. When testing on DG2, it is observed that this value is 0 when running test on some engines. To resolve that, get the hwe domain specific FW for reading the engine timestamp. v2: - update commit message - use domain specific FW (Matt) v3: - Drop check for hwe in the helper (Matt, Michal) v4: - checkpatch fixes v5: Rebase Fixes: 188ced1e0ff8 ("drm/xe/client: Print runtime to fdinfo") Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240627235105.2631135-1-umesh.nerlige.ramappa@intel.com
2024-06-28drm/nouveau: fix null pointer dereference in nouveau_connector_get_modesMa Ke
In nouveau_connector_get_modes(), the return value of drm_mode_duplicate() is assigned to mode, which will lead to a possible NULL pointer dereference on failure of drm_mode_duplicate(). Add a check to avoid npd. Cc: stable@vger.kernel.org Fixes: 6ee738610f41 ("drm/nouveau: Add DRM driver for NVIDIA GPUs") Signed-off-by: Ma Ke <make24@iscas.ac.cn> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240627074204.3023776-1-make24@iscas.ac.cn
2024-06-28drm/mediatek/dp: Fix spurious kfree()Michael Walle
drm_edid_to_sad() might return an error or just zero. If that is the case, we must not free the SADs because there was no allocation in the first place. Fixes: dab12fa8d2bd ("drm/mediatek/dp: fix memory leak on ->get_edid callback audio detection") Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20240604083337.1879188-1-mwalle@kernel.org/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2024-06-28drm/mediatek: dpi/dsi: Fix possible_crtcs calculationMichael Walle
mtk_find_possible_crtcs() assumes that the main path will always have the CRTC with id 0, the ext id 1 and the third id 2. This is only true if the paths are all available. But paths are optional (see also comment in mtk_drm_kms_init()), e.g. the main path might not be enabled or available at all. Then the CRTC IDs will shift one up, e.g. ext will be 0 and the third path will be 1. To fix that, dynamically calculate the IDs by the presence of the paths. While at it, make the return code a signed one and return -ENODEV if no path is found and handle the error in the callers. Fixes: 5aa8e7647676 ("drm/mediatek: dpi/dsi: Change the getting possible_crtc way") Suggested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://patchwork.kernel.org/project/dri-devel/patch/20240606092122.2026313-1-mwalle@kernel.org/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2024-06-28drm/i915/mtl: Skip PLL state verification in TBT modeImre Deak
In TBT-alt mode the driver doesn't program the PHY's PLL, which is handled instead by Thunderbolt driver/FW components, hence the PLL's HW vs. SW state verification should be skipped. During HW readout set a flag in the PLL state if the port was at the moment in TBT-alt mode and skip the verification of PLL parameters in this case. Fixes: 45fe957ae769 ("drm/i915/display: Add compare config for MTL+ platforms") Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11258 Cc: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240626170813.806470-1-imre.deak@intel.com
2024-06-28drm/stm: dsi: expose DSI PHY internal clockRaphael Gallais-Pou
DSISRC __________ __\_ | \ pll4_p_ck ->| 1 |____dsi_k ck_dsi_phy ->| 0 | |____/ A DSI clock is missing in the clock framework. Looking at the clk_summary, it appears that 'ck_dsi_phy' is not implemented. Since the DSI kernel clock is based on the internal DSI pll. The common clock driver can not directly expose this 'ck_dsi_phy' clock because it does not contain any common registers with the DSI. Thus it needs to be done directly within the DSI phy driver. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Tested-by: Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by: Philippe Cornu <philippe.cornu@foss.st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240129104106.43141-4-raphael.gallais-pou@foss.st.com
2024-06-28drm/stm: dsi: add pm runtime opsYannick Fertre
Update control of clocks and supply thanks to the PM runtime mechanism to avoid kernel crash during a system suspend. Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Tested-by: Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by: Philippe Cornu <philippe.cornu@foss.st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240129104106.43141-3-raphael.gallais-pou@foss.st.com
2024-06-28drm/stm: dsi: use new SYSTEM_SLEEP_PM_OPS() macroRaphael Gallais-Pou
Use RUNTIME_PM_OPS() instead of the old SET_SYSTEM_SLEEP_PM_OPS(). This means we don't need __maybe_unused on the functions. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Tested-by: Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by: Philippe Cornu <philippe.cornu@foss.st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240129104106.43141-2-raphael.gallais-pou@foss.st.com
2024-06-28drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driverRaphael Gallais-Pou
The Low-Voltage Differential Signaling (LVDS) Display Interface Transmitter handles the LVDS protocol: it maps the pixels received from the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS PHY. It is composed of three sub blocks: * LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input pixels onto the data lanes of the PHY * LVDS PHY: parallelize the data and drives the LVDS data lanes * LVDS wrapper: handles top-level settings The LVDS controller driver supports the following high-level features: * FDP-Link-I and OpenLDI (v0.95) protocols * Single-Link or Dual-Link operation * Single-Display or Double-Display (with the same content duplicated on both) * Flexible Bit-Mapping, including JEIDA and VESA * RGB888 or RGB666 output * Synchronous design, with one input pixel per clock cycle Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by: Philippe Cornu <philippe.cornu@foss.st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240226-lvds-v6-2-15e3463fbe70@foss.st.com
2024-06-28drm/panel: jd9365da: Add the function of adjusting orientationZhaoxiong Lv
This driver does not have the function to adjust the orientation, so this function is added. Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Link: https://lore.kernel.org/r/20240624141926.5250-6-lvzhaoxiong@huaqin.corp-partner.google.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240624141926.5250-6-lvzhaoxiong@huaqin.corp-partner.google.com
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-21 19:07:22 +0000