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2026-03-04drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailboxsguttula
The reason the RAP is not granting access to 0x58200 is that a dedicated RSMU slot would have to be spent for this address range, and MPASP is close to running out of RSMU slots. This will help to fix PSP TOC load failure during secureboot. GFX Driver Need to use indirect access for SMN address regs. Signed-off-by: sguttula <suresh.guttula@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amdgpu: Remove redundant missing hw ip handlingTvrtko Ursulin
Now that it is guaranteed there can be no entity if there is no hw ip block we can remove the open coded protection during CS parsing. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> References: 55414ad5c983 ("drm/amdgpu: error out on entity with no run queue") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amdgpu: Reject impossible entities earlyTvrtko Ursulin
Currently there are two different behaviour modes when userspace tries to operate on not present HW IP blocks. On a machine without UVD, VCE and VPE blocks, this can be observed for example like this: $ sudo ./amd_fuzzing --r cs-wait-fuzzing ... amd_cs_wait_fuzzing DRM_IOCTL_AMDGPU_CTX r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_GFX r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_COMPUTE r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_DMA r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_UVD r -1 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VCE r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_UVD_ENC r -1 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VCN_DEC r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VCN_ENC r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VCN_JPEG r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VPE r 0 We can see that UVD returns an errno (-EINVAL) from the CS_WAIT ioctl, while VCE and VPE return unexpected successes. The difference stems from the fact the UVD is a load balancing engine which retains the context, so with a workaround implemented in amdgpu_ctx_init_entity(), but which does not account for the fact hardware block may not be present. This causes a single NULL scheduler to be passed to drm_sched_entity_init(), which immediately rejects this with -EINVAL. The not present VCE and VPE cases on the other hand pass zero schedulers to drm_sched_entity_init(), which is explicitly allowed and results in unusable entities. As the UVD case however shows, call paths can handle the errors, so we can consolidate this into a single path which will always return -EINVAL if the HW IP block is not present. We do this by rejecting it early and not calling drm_sched_entity_init() when there is no backing hardware. This also removes the need for the drm_sched_entity_init() to handle the zero schedulers and NULL scheduler cases, which means that we can follow up by removing the special casing from the DRM scheduler. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> References: f34e8bb7d6c6 ("drm/sched: fix null-ptr-deref in init entity") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amdgpu/userq: refcount userqueues to avoid any race conditionsSunil Khatri
To avoid race condition and avoid UAF cases, implement kref based queues and protect the below operations using xa lock a. Getting a queue from xarray b. Increment/Decrement it's refcount Every time some one want to access a queue, always get via amdgpu_userq_get to make sure we have locks in place and get the object if active. A userqueue is destroyed on the last refcount is dropped which typically would be via IOCTL or during fini. v2: Add the missing drop in one the condition in the signal ioclt [Alex] v3: remove the queue from the xarray first in the free queue ioctl path [Christian] - Pass queue to the amdgpu_userq_put directly. - make amdgpu_userq_put xa_lock free since we are doing put for each get only and final put is done via destroy and we remove the queue from xa with lock. - use userq_put in fini too so cleanup is done fully. v4: Use xa_erase directly rather than doing load and erase in free ioctl. Also remove some of the error logs which could be exploited by the user to flood the logs [Christian] Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amdgpu: Fix use-after-free race in VM acquireAlysa Liu
Replace non-atomic vm->process_info assignment with cmpxchg() to prevent race when parent/child processes sharing a drm_file both try to acquire the same VM after fork(). Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alysa Liu <Alysa.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amd/pm: remove invalid gpu_metrics.energy_accumulator on smu v13.0.xYang Wang
v1: The metrics->EnergyAccumulator field has been deprecated on newer pmfw. v2: add smu 13.0.0/13.0.7/13.0.10 support. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amd/ras: adapt sync info func for pmfw eepromGangliang Xie
adapt sync info func for pmfw eeprom Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amd/ras: add check func for pmfw eepromGangliang Xie
add check func for pmfw eeprom Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amdgpu: GFX12.1 scratch memory limit up to 57-bitPhilip Yang
The scratch aperture or gmc private aperture in flat memory contains 57 bits of data on gfx v12.1.0 compared to the 32 bits from previous. Add new helper kfd_init_apertures_v12 for gfx version >= v12.1.0 which supports 57-bit VA space. v2: - update pdd->scratch_limit (Yu, Lang) - update fixes tag (Felix Kuehling) - add helper kfd_init_apertures_v12 Fixes: db1882b3ff0c ("drm/amdkfd: Update LDS, Scratch base for 57bit address") Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Lang Yu <lang.yu@amd.com> Acked-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amd/ras: add initialization func for pmfw eepromGangliang Xie
add initialization func for pmfw eeprom Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amd/ras: adapt page retirement process for pmfw eepromGangliang Xie
read bad page data from pmfw eeprom when retirement is triggered, use timestamp read from eeprom Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amd/ras: add read func for pmfw eepromGangliang Xie
add read func for pmfw eeprom, and adapt address converting for bad pages loaded from pmfw eeprom v2: change label 'Out' to 'out' Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amd/ras: make MCA IPID parse globalTao Zhou
add a new IPID parse interface for umc, so we can implement it for each ASIC, and so we can call it in other blocks Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amd/ras: add append func for pmfw eepromGangliang Xie
add append func for pmfw eeprom Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amd/ras: add check safety watermark func for pmfw eepromGangliang Xie
add check safety watermark func for pmfw eeprom Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/xe: Fix memory leak in xe_vm_madvise_ioctlVarun Gupta
When check_bo_args_are_sane() validation fails, jump to the new free_vmas cleanup label to properly free the allocated resources. This ensures proper cleanup in this error path. Fixes: 293032eec4ba ("drm/xe/bo: Update atomic_access attribute on madvise") Cc: stable@vger.kernel.org # v6.18+ Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com> Signed-off-by: Varun Gupta <varun.gupta@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260223175145.1532801-1-varun.gupta@intel.com Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> (cherry picked from commit 29bd06faf727a4b76663e4be0f7d770e2d2a7965) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-03-04drm/xe/reg_sr: Fix leak on xa_store failureShuicheng Lin
Free the newly allocated entry when xa_store() fails to avoid a memory leak on the error path. v2: use goto fail_free. (Bala) Fixes: e5283bd4dfec ("drm/xe/reg_sr: Remove register pool") Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260204172810.1486719-2-shuicheng.lin@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> (cherry picked from commit 6bc6fec71ac45f52db609af4e62bdb96b9f5fadb) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-03-04drm/xe/xe2_hpg: Correct implementation of Wa_16025250150Matt Roper
Wa_16025250150 asks us to set five register fields of the register to 0x1 each. However we were just OR'ing this into the existing register value (which has a default of 0x4 for each nibble-sized field) resulting in final field values of 0x5 instead of the desired 0x1. Correct the RTP programming (use FIELD_SET instead of SET) to ensure each field is assigned to exactly the value we want. Cc: Aradhya Bhatia <aradhya.bhatia@intel.com> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com> Cc: stable@vger.kernel.org # v6.16+ Fixes: 7654d51f1fd8 ("drm/xe/xe2hpg: Add Wa_16025250150") Reviewed-by: Ngai-Mint Kwan <ngai-mint.kwan@linux.intel.com> Link: https://patch.msgid.link/20260227164341.3600098-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> (cherry picked from commit d139209ef88e48af1f6731cd45440421c757b6b5) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-03-04drm/xe/gsc: Fix GSC proxy cleanup on early initialization failureZhanjun Dong
xe_gsc_proxy_remove undoes what is done in both xe_gsc_proxy_init and xe_gsc_proxy_start; however, if we fail between those 2 calls, it is possible that the HW forcewake access hasn't been initialized yet and so we hit errors when the cleanup code tries to write GSC register. To avoid that, split the cleanup in 2 functions so that the HW cleanup is only called if the HW setup was completed successfully. Since the HW cleanup (interrupt disabling) is now removed from xe_gsc_proxy_remove, the cleanup on error paths in xe_gsc_proxy_start must be updated to disable interrupts before returning. Fixes: ff6cd29b690b ("drm/xe: Cleanup unwind of gt initialization") Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patch.msgid.link/20260220225308.101469-1-zhanjun.dong@intel.com (cherry picked from commit 2b37c401b265c07b46408b5cb36a4b757c9b5060) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-03-04Revert "drm/pagemap: Disable device-to-device migration"Thomas Hellström
With commit a69d1ab971a6 ("mm: Fix a hmm_range_fault() livelock / starvation problem") device-to-device migration is not functional again and the disabling can be reverted. Add the above commit as a Fixes: tag in order for the revert to not take place unless that commit is present. This reverts commit 10dd1eaa80a56d3cf6d7c36b5269c8fed617f001. Cc: Matthew Brost <matthew.brost@intel.com> Fixes: b570f37a2ce4 ("mm: Fix a hmm_range_fault() livelock / starvation problem") Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260211104159.114947-1-thomas.hellstrom@linux.intel.com (cherry picked from commit 1a3c0049b3f56278c9caf2784c53f6ab435fd12c) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Rodrigo updated Fixes tag]
2026-03-04drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTLVille Syrjälä
Apparently ICL may hang with an MCE if we write TRANS_VRR_VMAX/FLIPLINE before enabling TRANS_DDI_FUNC_CTL. Personally I was only able to reproduce a hang (on an Dell XPS 7390 2-in-1) with an external display connected via a dock using a dodgy type-C cable that made the link training fail. After the failed link training the machine would hang. TGL seemed immune to the problem for whatever reason. BSpec does tell us to configure VRR after enabling TRANS_DDI_FUNC_CTL as well. The DMC firmware also does the VRR restore in two stages: - first stage seems to be unconditional and includes TRANS_VRR_CTL and a few other VRR registers, among other things - second stage is conditional on the DDI being enabled, and includes TRANS_DDI_FUNC_CTL and TRANS_VRR_VMAX/VMIN/FLIPLINE, among other things So let's reorder the steps to match to avoid the hang, and toss in an extra WARN to make sure we don't screw this up later. BSpec: 22243 Cc: stable@vger.kernel.org Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reported-by: Benjamin Tissoires <bentiss@kernel.org> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15777 Tested-by: Benjamin Tissoires <bentiss@kernel.org> Fixes: dda7dcd9da73 ("drm/i915/vrr: Use fixed timings for platforms that support VRR") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260303095414.4331-1-ville.syrjala@linux.intel.com Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
2026-03-04drm/i915/psr: Fix for Panel Replay X granularity DPCD register handlingJouni Högander
DP specification is saying value 0xff 0xff in PANEL REPLAY SELECTIVE UPDATE X GRANULARITY CAPABILITY registers (0xb2 and 0xb3) means full-line granularity. Take this into account when handling Panel Replay X granularity informed by the panel. Fixes: 1cc854647450 ("drm/i915/psr: Use SU granularity information available in intel_connector") Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/7284 Tested-by: Mark Pearson <mpearson-lenovo@squebb.ca> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20260225074221.1744330-2-jouni.hogander@intel.com (cherry picked from commit f5c8f824a495e849492f09a43bd965a8f4d86cb2) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2026-03-04drm/i915/gt: prefer _PICK_EVEN() over _PICK()Jani Nikula
There's no need to use _PICK() here. Use the simpler one instead. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/f94272fb9e93afa51d9fdb006888b8ebe38580df.1772042022.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-04drm/intel: add pick.h for the various "picker" helpersJani Nikula
Add a shared header that's used by i915, xe, and i915 display. This allows us to drop the compat-i915-headers/i915_reg_defs.h include from xe_reg_defs.h. All the register macro helpers were subtly pulled in from i915 to all of xe through this. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/fcd70f3317755bf98a6e7ae88974aa8ba06efd1e.1772042022.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-04drm/intel: add reg_bits.h for the various register content helpersJani Nikula
Add a shared header that's used by i915, xe, and i915 display. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/e641fe6dcecef92367471f3e0d150f9f47ae4edc.1772042022.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-04drm/xe/oa: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE()Jani Nikula
Using REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() is more obvious to the reader than having the ternary expression inside REG_MASKED_FIELD(). Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/a9b0151d82b1622daa0625fc8ea2c41d233e4318.1772042022.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-04drm/i915/perf: prefer REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE()Jani Nikula
Using REG_MASKED_FIELD_ENABLE() and REG_MASKED_FIELD_DISABLE() is more obvious to the reader than having the ternary expression inside REG_MASKED_FIELD(). Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/93caec439ad10ef8b163162c52407abf36df69f5.1772042022.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-04drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*()Jani Nikula
The underscore prefixed masked field helper names aren't great. Rename them REG_MASKED_FIELD(), REG_MASKED_FIELD_ENABLE(), and REG_MASKED_FIELD_DISABLE(). This is more in line with the existing REG_FIELD_PREP() etc. helpers, and using "field" instead of "bit" is more accurate for the functionality. This is done with: sed -i 's/_MASKED_FIELD/REG_MASKED_FIELD/g' $(git grep -wl _MASKED_FIELD) sed -i 's/_MASKED_BIT_ENABLE/REG_MASKED_FIELD_ENABLE/g' $(git grep -wl _MASKED_BIT_ENABLE) sed -i 's/_MASKED_BIT_DISABLE/REG_MASKED_FIELD_DISABLE/g' $(git grep -wl _MASKED_BIT_DISABLE) with some manual indentation fixes on top. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/49dc20448a12f3e03f5f8347540d167a281b8987.1772042022.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-04drm/i915/lrc: switch to _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE()Jani Nikula
Since it's now possible to use _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() in the array initializer, switch to them. This allows us to remove __MASKED_FIELD() macro. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/733568f8a6155b6e2da1dcdce9d21d6aab881449.1772042022.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-04drm/i915/reg: make masked field helpers constexprJani Nikula
Make it possible to use _MASKED_FIELD(), _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() in contexts that require integer constant expressions. This increases their usefulness at the small cost of making the warnings from build time checks less helpful. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/788f538cc71dec0db25e0c768e8945bef6f9701c.1772042022.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-04drm/ttm/tests: Fix build failure on PREEMPT_RTMaarten Lankhorst
Fix a compile error in the kunit tests when CONFIG_PREEMPT_RT is enabled, and the normal mutex is converted into a rtmutex. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202602261547.3bM6yVAS-lkp@intel.com/ Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patch.msgid.link/20260304085616.1216961-1-dev@lankhorst.se Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
2026-03-04drm/imagination: Ensure struct pvr_device->power is initializedMatt Coster
When pvr_power_domains_init() handles <=1 power domains, the content of struct pvr_device->power was previously left uninitialized. Fixes: e19cc5ab347e3 ("drm/imagination: Use dev_pm_domain_attach_list()") Reviewed-by: Alessio Belle <alessio.belle@imgtec.com> Link: https://patch.msgid.link/20260227-single-domain-power-fixes-v1-3-d37ba0825f7c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-03-04drm/imagination: Detach pm domains if linking failsMatt Coster
There's a missing call to dev_pm_domain_detach_list() in the error path of pvr_power_domains_init(); if creating the second stage of device links fails then the struct dev_pm_domain_list will be left dangling. Fixes: e19cc5ab347e3 ("drm/imagination: Use dev_pm_domain_attach_list()") Reviewed-by: Alessio Belle <alessio.belle@imgtec.com> Link: https://patch.msgid.link/20260227-single-domain-power-fixes-v1-2-d37ba0825f7c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-03-04drm/imagination: Check for NULL struct dev_pm_domain_listMatt Coster
While dev_pm_domain_detach_list() itself contains the necessary NULL check, the access to struct dev_pm_domain_list->num_pds does not and thus faults on devices with <=1 power domains (where the struct dev_pm_domain_list machinery is skipped for simplicity). This can be reproduced on AM625, which produces the following log[1]: [ 10.820056] powervr fd00000.gpu: Direct firmware load for powervr/rogue_33.15.11.3_v1.fw failed with error -2 [ 10.831903] powervr fd00000.gpu: [drm] *ERROR* failed to load firmware powervr/rogue_33.15.11.3_v1.fw (err=-2) ... [ 10.844023] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000018 ... [ 11.090162] Call trace: [ 11.092600] pvr_power_domains_fini+0x18/0xa0 [powervr] (P) [ 11.098218] pvr_probe+0x100/0x14c [powervr] [ 11.102505] platform_probe+0x5c/0xa4 Fixes: e19cc5ab347e3 ("drm/imagination: Use dev_pm_domain_attach_list()") Reported-by: Mark Brown <broonie@kernel.org> Closes: https://lore.kernel.org/r/c353fdef-9ccd-4a11-a527-ab4a792d8e70@sirena.org.uk/ [1] Tested-by: Mark Brown <broonie@kernel.org> Reviewed-by: Alessio Belle <alessio.belle@imgtec.com> Link: https://patch.msgid.link/20260227-single-domain-power-fixes-v1-1-d37ba0825f7c@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-03-04drm/i915/psr: Fix for Panel Replay X granularity DPCD register handlingJouni Högander
DP specification is saying value 0xff 0xff in PANEL REPLAY SELECTIVE UPDATE X GRANULARITY CAPABILITY registers (0xb2 and 0xb3) means full-line granularity. Take this into account when handling Panel Replay X granularity informed by the panel. Fixes: 1cc854647450 ("drm/i915/psr: Use SU granularity information available in intel_connector") Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/7284 Tested-by: Mark Pearson <mpearson-lenovo@squebb.ca> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20260225074221.1744330-2-jouni.hogander@intel.com
2026-03-04drm/sched: Fix kernel-doc warning for drm_sched_job_done()Yujie Liu
There is a kernel-doc warning for the scheduler: Warning: drivers/gpu/drm/scheduler/sched_main.c:367 function parameter 'result' not described in 'drm_sched_job_done' Fix the warning by describing the undocumented error code. Fixes: 539f9ee4b52a ("drm/scheduler: properly forward fence errors") Signed-off-by: Yujie Liu <yujie.liu@intel.com> [phasta: Flesh out commit message] Signed-off-by: Philipp Stanner <phasta@kernel.org> Link: https://patch.msgid.link/20260227082452.1802922-1-yujie.liu@intel.com
2026-03-03drm/msm: Fix dma_free_attrs() buffer sizeThomas Fourier
The gpummu->table buffer is alloc'd with size TABLE_SIZE + 32 in a2xx_gpummu_new() but freed with size TABLE_SIZE in a2xx_gpummu_destroy(). Change the free size to match the allocation. Fixes: c2052a4e5c99 ("drm/msm: implement a2xx mmu") Cc: <stable@vger.kernel.org> Signed-off-by: Thomas Fourier <fourier.thomas@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/707340/ Message-ID: <20260226095714.12126-2-fourier.thomas@gmail.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-03-03drm/msm/a6xx: Fix the bogus protect error on X2-85Akhil P Oommen
Update the X2-85 gpu's register protect count configuration with the correct count_max value to avoid blocking the entire MMIO region from the UMD. Protect configurations are a bit complicated on A8xx. There are 2 set of protect registers with different counts: Global and Pipe-specific. The last-span-unbound feature is available only on the Pipe-specific protect registers. Due to this, we cannot use the BUILD_BUG sanity check for A8x protect configurations, so remove the A840 entry from there. Fixes: 01ff3bf27215 ("drm/msm/a8xx: Add support for Adreno X2-85 GPU") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/706944/ Message-ID: <20260225-glymur-protect-fix-v1-1-0deddedf9277@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-03-03drm/i915/overlay: Fix oops on unloadVille Syrjälä
Apparently I failed to test the unload case properly and thus didn't notice that the i915_overlay_is_active() needs i915->overlay after fetch_and_zero() already cleared it. Stop using fetch_and_zero() and only clear the pointer at the end to avoid the oops. Fixes: 38d9a352c45e ("drm/i915/overlay: Extract i915_overlay_is_active()") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260303101417.14409-1-ville.syrjala@linux.intel.com Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
2026-03-03drm/i915/dp: Ack only the handled link service IRQsImre Deak
Ack only those SST link service IRQs that will be handled, similarly to device service IRQs. While at it add asserts that only the known/acked link service IRQs are handled both in the MST and SST case. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-21-imre.deak@intel.com
2026-03-03drm/i915/dp: Ack only the handled device service IRQsImre Deak
Only those IRQs should be acked that are handled, however for SST all IRQs triggered by the sink are acked. This can be a problem for flags that are reserved/reading zero at a given moment, but become used for some purpose - with a side-effect if set - in a future DPCD revision. Fix the above by acking only those device service IRQs that will be handled. While at it add asserts that only the known/acked device service IRQs are handled both in the MST and SST case. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-20-imre.deak@intel.com
2026-03-03drm/i915/dp_mst: Reuse intel_dp_handle_link_service_irq()Imre Deak
Use intel_dp_handle_link_service_irq() while handling an MST HPD IRQ, instead of open-coding this. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-19-imre.deak@intel.com
2026-03-03drm/i915/dp: Check SST link status while handling link service IRQsImre Deak
Move checking the link status for SST to intel_dp_handle_link_service_irq(). This is the logical place for the check which should only happen in response to a LINK_STATUS_CHANGE sink IRQ. This IRQ is only supported by DPCD revision >= 1.2, so for sinks with an older DPCD revision the link status is checked in response to any HPD IRQ. For newer DPCD revisions however the link status check can be made conditional on LINK_STATUS_CHANGE. For now keep the current behavior of always forcing a link status check regardless of LINK_STATUS_CHANGE being set or not. This also prepares for a follow-up change sharing the link service IRQ handler for SST and MST (on MST the link status check only happening in response to a LINK_STATUS_CHANGE IRQ). Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-18-imre.deak@intel.com
2026-03-03drm/i915/dp: Print debug message for a sink connected off requestImre Deak
So far the CONNECTED_OFF_ENTRY_REQUESTED request was accepted only implicitly, by acking all the IRQs raised by the sink. Make this explicit by printing a debug message. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-17-imre.deak@intel.com
2026-03-03drm/i915/dp: Read/ack sink count and sink IRQs for SST as it's done for MSTImre Deak
Read and ack the sink count, sink device and link service IRQs for SST the same way this is done for MST, the read/ack happening in separate steps via an ESI (Event Status Indicator) vector. The above way is more efficient, since on newer (DPCD_REV >= 1.2) sinks the DP_SINK_COUNT_ESI..DP_LINK_SERVICE_IRQ_VECTOR_ESI0 registers can be read out in one AUX transaction - and the 3 last one written in one transaction. Also this allows sharing more of the SST and MST IRQ handling code (done as a follow-up). For now keep the current behavior of always reading the legacy DP_SINK_COUNT, DP_DEVICE_SERVICE_IRQ_VECTOR registers and not reading the DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 register. v2: Document the ESI vector get/ack helper fnuctions' return value. (Jani, Luca) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-16-imre.deak@intel.com
2026-03-03drm/i915/dp: Return early if getting/ackink link service IRQs failsImre Deak
If getting/acking the link service IRQs fail, the short HPD handler should bail out, falling back to a full connector detection as in case of any AUX access failures during the HPD handling. Do this by separating the getting/acking and handling steps of the IRQs. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-15-imre.deak@intel.com
2026-03-03drm/i915/dp: Return early if getting/acking device service IRQs failsImre Deak
If getting/acking the device service IRQs fail, the short HPD handler should bail out, falling back to a full connector detection as in case of any AUX access failures during the HPD handling. Do this by separating the getting/acking and handling steps of the IRQs. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-14-imre.deak@intel.com
2026-03-03drm/i915/dp: Reprobe connector if getting/acking link service IRQs failsImre Deak
An AUX access failure during HPD IRQ handling should be handled by falling back to a full connector detection, ensure that if the failure happens while reading/acking a link service IRQ. While at it add code comment documenting the return value of intel_dp_check_link_service_irq(). v2: Docuement intel_dp_check_link_service_irq()'s return value. (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-13-imre.deak@intel.com
2026-03-03drm/i915/dp: Reprobe connector if getting/acking device IRQs failsImre Deak
An AUX access failure during HPD IRQ handling should be handled by falling back to a full connector detection, ensure that if the failure happens while reading/acking a device service IRQ. v2: Document intel_dp_check_device_service_irq()'s return value. (Jani, Luca) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-12-imre.deak@intel.com
2026-03-03drm/i915/dp: Fix the link service IRQ DPCD_REV checkImre Deak
The DP_LINK_SERVICE_IRQ_VECTOR_ESI0 DPCD register is supported only since DPCD REV 1.2, so fix the revision check accordingly. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260225164618.1261368-11-imre.deak@intel.com
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-09 03:25:25 +0000