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2026-03-20arm64: dts: broadcom: bcm2712: Move non simple-bus nodes to root levelRob Herring (Arm)
The 'gpu' and 'firmware' nodes are not MMIO devices, so they should not be under a 'simple-bus', but at the root level. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260320154809.1246064-2-robh@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-03-16arm64: dts: broadcom: bcm2712-d-rpi-5-b: update uart10 interruptGregor Herburger
On the -d revision of bcm2712 the uart interrupt is on 120. Update it accordingly. Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de> Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-6-60832d20ff04@linutronix.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-03-16arm64: dts: broadcom: bcm2712-d-rpi-5-b: add fixes for pinctrl/pinctrl_aonGregor Herburger
On the -d revision of the bcm2712 the pinctrl differs from the c0 revision. The driver already supports both and distinguishes the two with the compatible string. Update the compatible string and reg length to reflect the different pinctrl. Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de> Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-5-60832d20ff04@linutronix.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-03-16arm64: dts: broadcom: bcm2712-rpi-5-b: add pinctrl properties for csi i2csGregor Herburger
Configure the i2c pins for the csi interfaces as i2c. Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de> Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-4-60832d20ff04@linutronix.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-03-16arm64: dts: broadcom: bcm2712: add camera backend node pispbeGregor Herburger
The bcm2712 found in the Raspberry Pi 5 has a PiSP Image Signal Processor back end image processor. Add the relevant node to the devicetree. Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de> Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-3-60832d20ff04@linutronix.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-03-16arm64: dts: broadcom: rp1: add csi nodesGregor Herburger
The RaspberryPi 5 has 2 PiSP Camera front end controller on the RP1 chipset. Add the relevant nodes to the devicetree. Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de> Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-2-60832d20ff04@linutronix.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-03-16arm64: dts: broadcom: rp1: add i2c controllerGregor Herburger
The RaspberryPi 5 has 7 designware-i2c I2C controller on the RP1 chipset. Add the relevant nodes to the devicetree. Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de> Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-1-60832d20ff04@linutronix.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-03-16arm64: dts: broadcom: bcm2712: Add V3D device nodeMaíra Canal
Commits 0ad5bc1ce463 ("drm/v3d: fix up register addresses for V3D 7.x") and 6fd9487147c4 ("drm/v3d: add brcm,2712-v3d as a compatible V3D device") added driver support for V3D on BCM2712, but the corresponding device tree node is still missing. Add the V3D device tree node to the BCM2712 DTS. Signed-off-by: Maíra Canal <mcanal@igalia.com> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20260114120610.82531-1-mcanal@igalia.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-02-10Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "There are a handful of new SoCs this time, all of these are more or less related to chips in a wider family: - SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first widely available RVA23 implementation. Note that this is entirely unrelated with the similarly named Texas Instruments K3 chip family that follwed the TI Keystone2 SoC. - The Realtek Kent family of SoCs contains three chip models rtd1501s, rtd1861b and rtd1920s, and is related to their earlier Set-top-box and NAS products such as rtd1619, but is built on newer Arm Cortex-A78 cores. - The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635) mobile phone SoC built around Armv9 Kryo cores of the Arm Cortex-A720 generation. This one is used in the Fairphone Gen 6 - Qualcomm Kaanapali is a new SoC based around eight high performance Oryon CPU cores - NXP i.MX8QP and i.MX952 are both feature reduced versions of chips we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU cores and I/O interfaces. As part of a cleanup, a number of SoC specific devicetree files got removed because they did not have a single board using the .dtsi files and they were never compile tested as a result: Samsung s3c6400, ST spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/ r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI am3703/am3715. All of these could be restored easily if a new board gets merged. Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only machine, as all remaining users are assumed to be using ACPI based firmware. A relatively small number of 43 boards get added this time, and almost all of them for arm64. Aside from the reference boards for the newly added SoCs, this includes: - Three server boards use 32-bit ASpeed BMCs - One more reference board for 32-bit Microchip LAN9668 - 64-bit Arm single-board computers based on Amlogic s905y4, CIX sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm qcs6490/qrb2210 and Rockchip rk3568/rk3588s - Carrier board for SOMs using Intel agilex5, Marvell Armada 7020, NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588 - Two mobile phones using Snapdragon 845 - A gaming device and a NAS box, both based on Rockchips rk356x On top of the newly added boards and SoCs, there is a lot of background activity going into cleanups, in particular towards getting a warning-free dtc build, and the usual work on adding support for more hardware on the previously added machines" * tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits) dt-bindings: intel: Add Agilex eMMC support arm64: dts: socfpga: agilex: add emmc support arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node ARM: dts: socfpga: fix dtbs_check warning for fpga-region ARM: dts: socfpga: add #address-cells and #size-cells for sram node dt-bindings: altera: document syscon as fallback for sys-mgr arm64: dts: altera: Use lowercase hex dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes arm64: dts: socfpga: agilex5: add support for modular board dt-bindings: intel: Add Agilex5 SoCFPGA modular board arm64: dts: socfpga: agilex5: Add dma-coherent property arm64: dts: realtek: Add Kent SoC and EVB device trees dt-bindings: arm: realtek: Add Kent Soc family compatibles ARM: dts: samsung: Drop s3c6400.dtsi ARM: dts: nuvoton: Minor whitespace cleanup MAINTAINERS: Add Falcon DB arm64: dts: a7k: add COM Express boards ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi arm64: dts: rockchip: Fix rk3588 PCIe range mappings ...
2026-01-16arm64: dts: broadcom: bcm4906-netgear-r8000p: Drop unnecessary "ranges" in ↵Rob Herring (Arm)
partition node "ranges" is only valid for MMIO addresses as it is used for translating addresses to CPU address. Even if a partial translation was supported, the DT is incorrect here as the nvmem-layout node would also need "ranges". So drop "ranges" and the associated cell size properties. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260108231558.1422454-2-robh@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: northstar2: Drop "arm,cci-400-pmu" fallback compatibleRob Herring (Arm)
The "arm,cci-400-pmu" compatible is not documented as a valid fallback nor is it used, so drop it. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-13-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: northstar2: Drop QSPI "clock-names"Rob Herring (Arm)
The "clock-names" property is not documented for the "brcm,spi-bcm-qspi" binding nor in use by the kernel driver, so drop it. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-12-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: northstar2: Drop unused and undocumented ↵Rob Herring (Arm)
"brcm,pcie-ob-oarr-size" properties The "brcm,pcie-ob-oarr-size" property is unused and undocumented, so drop them. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-11-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: northstar2: Rework clock nodesRob Herring (Arm)
The nd2-clocks.dtsi is oddly included in the middle of a bus node and is only included in one place, so collapse it into ns2.dtsi. Move the fixed and fixed-factor clock nodes to the root as they are not part of the bus. Rename the node names to use preferred names. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-10-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: ns2-svk: Use non-deprecated at25 propertiesRob Herring (Arm)
The at25,* properties have been deprecated since 2012. This board wasn't upstream until 2014, so it should be safe to switch over to the "new" properties. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-9-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: Use preferred node namesRob Herring (Arm)
Update various node names to use the documented preferred names. Node names/path aren't considered ABI, so changing them should be safe. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-8-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: stingray: Move raid nodes out of busRob Herring (Arm)
The 'raid' nodes are not MMIO devices and are not part of a bus, so move them to the root level. Drop the unit-addresses as they don't have any address. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-7-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: stingray: Fix 'simple-bus' node namesRob Herring (Arm)
Fix 'simple-bus' node names to follow the defined pattern. Nodes with 'reg' or 'ranges' addresses should also have a unit-address. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-6-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: stingray: Rework clock nodesRob Herring (Arm)
The stringray-clocks.dtsi is oddly included in the middle of a bus node and is only included in one place, so collapse it into stingray.dtsi. Move the fixed and fixed-factor clock nodes to the root as they are not part of the bus. Rename the node names to use preferred names. Drop the unnecessary 1:1 fixed-factor clock providers. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-5-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-16arm64: dts: broadcom: Remove unused and undocumented nodesRob Herring (Arm)
The "silabs,si3226x" and "brcm,bdc-v0.16" nodes have no documentation and no driver in the kernel, so remove them. They can be added back with proper documentation if there is a need for them. Note that if both USB ports have similar memory maps in relationship to their USB PHY nodes, it looks like the device controller should have been at 0x12000, not 0x21000? Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-4-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-08arm64: dts: broadcom: bcm2712: Add watchdog DT nodeStanimir Varbanov
Add watchdog device-tree node for bcm2712 SoC. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> Link: https://lore.kernel.org/r/20251031183309.1163384-5-svarbanov@suse.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-08arm64: dts: broadcom: bcm2712: Enable RNGPeter Robinson
The RNG is the same IP as in the bcm2711 so add the device tree block to enable the device. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20250927075643.716179-1-pbrobinson@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-12-19arm64: dts: broadcom: rp1: drop RP1 overlayAndrea della Porta
RP1 support loaded from overlay has been dropped from the driver and the DTB intended to be loaded with the overlay no longer exists. Drop unused include file and overlay. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/85167b815d41ed9ed690ad239a19de5cd2e8be1c.1766077285.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-12-19arm64: dts: broadcom: bcm2712: fix RP1 endpoint PCI topologyAndrea della Porta
The node describing the RP1 endpoint currently uses a specific name ('rp1_nexus') that does not correctly reflect the PCI topology. Update the DT with the correct topology and use generic node names. Additionally, since the driver dropped overlay support in favor of a fully described DT, rename '...-ovl-rp1.dts' to '...-base.dtsi' for inclusion in the board DTB, as it is no longer compiled as a standalone DTB. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/827b12ba48bb47bc77a0f5e5617aea961c8bc6b5.1766077285.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-11-05arm64: dts: broadcom: bcm2712: rpi-5: Add ethernet0 aliasLaurent Pinchart
The RP1 ethernet controller DT node contains a local-mac-address property to pass the MAC address from the boot loader to the kernel. The boot loader does not fill the MAC address as the ethernet0 alias is missing. Add it. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/20251102111443.18206-1-laurent.pinchart@ideasonboard.com Fixes: 43456fdfc014 ("arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5") Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-11-05arm64: dts: broadcom: Assign clock rates in eth node for RPi5Andrea della Porta
In Raspberry Pi 5 DTS, the Ethernet clock rates must be assigned as the default clock register values are not valid for the Ethernet interface to function. This can be done either in rp1_clocks node or in rp1_eth node. Define the rates in rp1_eth node, as those clocks are 'leaf' clocks used specifically by the Ethernet device only. Fixes: 43456fdfc014 ("arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5") Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/20251021135533.5517-1-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-10-13arm64: dts: broadcom: bcm2712: Define VGIC interruptPeter Robinson
Define the interrupt in the GICv2 for vGIC so KVM can be used, it was missed from the original upstream DTB for some reason. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Andrea della Porta <andrea.porta@suse.com> Cc: Phil Elwell <phil@raspberrypi.com> Fixes: faa3381267d0 ("arm64: dts: broadcom: Add minimal support for Raspberry Pi 5") Link: https://lore.kernel.org/r/20250924085612.1039247-1-pbrobinson@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-09arm64: dts: broadcom: Enable USB devicetree entries for Rpi5Andrea della Porta
RaspberryPi 5 presents two USB 2.0 and two USB 3.0 ports. Configure and enable the USB nodes in the devicetree. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/c6b17f0f896b5cdd790fc10aeb2b76b71df9b58d.1757065053.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-09arm64: dts: broadcom: rp1: Add USB nodesAndrea della Porta
The RaspberryPi 5 has RP1 chipset containing two USB host controller, while presenting two USB 2.0 and two USB 3.0 ports to the outside. Add the relevant USB nodes to the devicetree. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/16d753cb4bf37beb5e9c6f0e03576cf13708f27d.1757065053.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-04arm64: dts: broadcom: amend the comment about the role of BCM2712 board DTSAndrea della Porta
Current board DTS for Raspberry Pi5 states that bcm2712-rpi-5-b.dts should not be modified and all declarations should go in the overlay board DTS instead (bcm2712-rpi-5-b-ovl-rp1.dts). There's a caveat though: there's currently no infrastructure to reliably reference nodes that have not been declared yet, as is the case when loading those nodes from a runtime overlay. For more details about these limitations see [1] and follow-ups. Change the comment to make it clear which DTS file will host specific nodes, especially the RP1 related nodes which should be customized outside the overlay DTS. Link [1] - https://lore.kernel.org/all/CAMEGJJ3=W8_R0xBvm8r+Q7iExZx8xPBHEWWGAT9ngpGWDSKCaQ@mail.gmail.com/ Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/47f6368a77d6bd846c02942d20c07dd48e0ae7df.1754914766.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-04arm64: dts: broadcom: delete redundant pcie enablement nodesAndrea della Porta
The pcie1 and pcie2 override nodes to enable the respective peripherals are declared both in bcm2712-rpi-5-b.dts and bcm2712-rpi-5-b-ovl-rp1.dts, which makes those declared in the former file redundant. Drop those redundant nodes from the board devicetree. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/2865b787d893fd1dcf816e1c96856711754d612d.1754914766.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-04arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5Stanimir Varbanov
Enable RP1 ethernet DT node for Raspberry Pi 5. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20250822093440.53941-6-svarbanov@suse.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-04arm64: dts: rp1: Add ethernet DT nodeStanimir Varbanov
Add macb GEM ethernet DT node. Signed-off-by: Stanimir Varbanov <svarbanov@suse.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20250822093440.53941-5-svarbanov@suse.de Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-04arm64: dts: broadcom: bcm2712: Add UARTA controller nodeIvan T. Ivanov
On RPi5 device Bluetooth chips is connected to UARTA port. Add Bluetooth chips and related pin definitions. With this and firmware already provided by distributions, at least on openSUSE Tumbleweed, this is sufficient to make Bluetooth operational on RPi5 \o/. Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/35c0da6a741019efefc3c8e405e210a3a8156830.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-04arm64: dts: broadcom: bcm2712: Add second SDHCI controller nodeIvan T. Ivanov
Add SDIO2 node. On RPi5 it is connected to WiFi chip. Add related pin, gpio and regulator definitions and add WiFi node. With this and firmware already provided by distributions, at least on openSUSE Tumbleweed, this is sufficient to make WiFi operational on RPi5 \o/. Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/4ff3a58e98d90a43deb2448b23754808afc7153b.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-04arm64: dts: broadcom: bcm2712: Add one more GPIO nodeIvan T. Ivanov
Add GPIO and related interrupt controller nodes and wire one of the lines to power button. Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/6d311b2f629bbc0e1dd9821e4aa8e5af9f8e5362.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-04arm64: dts: broadcom: bcm2712: Add pin controller nodesIvan T. Ivanov
Add pin-control devicetree nodes and used them to explicitly define uSD card interface pin configuration. Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/5ceba8558e0007a9685f19b51d681d0ce79e7634.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-09-03arm64: dts: broadcom: bcm2712: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: bcm2712.dtsi:494.4-497.31: Warning (interrupt_map): /axi/pcie@1000110000:interrupt-map: Missing property '#address-cells' in node /soc@107c000000/interrupt-controller@7fff9000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250822133407.312505-2-krzysztof.kozlowski@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-10arm64: dts: broadcom: northstar2: Drop GIC V2M "interrupt-parent"Rob Herring (Arm)
The default interrupt parent is a parent node containing "#interrupt-cells", so an explicit "interrupt-parent" is not necessary. Fixes these dtschema warnings: (arm,gic-400): v2m@70000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@60000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@50000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@40000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@30000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@20000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@10000: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' (arm,gic-400): v2m@0: 'interrupt-parent' does not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250609203705.2852500-1-robh@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09arm64: dts: broadcom: Add overlay for RP1 deviceAndrea della Porta
Define the RP1 node in an overlay. The inclusion tree is as follow (the arrow points to the includer): rp1.dtso ^ | rp1-common.dtsi ----> rp1-nexus.dtsi Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-10-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09arm64: dts: broadcom: Add board DTS for Rpi5 which includes RP1 nodeAndrea della Porta
Add the fully populated DTS for RaspberryPi 5 which includes the RP1 node definition. The inclusion tree is as follow (the arrow points to the includer): rp1-common.dtsi ----> rp1-nexus.dtsi ----> bcm2712-rpi-5-b.dts ^ | bcm2712-rpi-5-b-ovl-rp1.dts This is designed to maximize the compatibility with downstream DT while ensuring that a fully defined DT (one which includes the RP1 node as opposed to load it from overlay at runtime) is present since early boot stage. Since the preferred board DT is the fully populated one, name it bcm2712-rpi-5-b.dts and move the previous one into bcm2712-rpi-5-b-ovl-rp1.dts. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/r/20250529135052.28398-9-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09arm64: dts: bcm2712: Add external clock for RP1 chipset on Rpi5Andrea della Porta
The RP1 found on Raspberry Pi 5 board needs an external crystal at 50MHz. Add clk_rp1_xosc node to provide that. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-8-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09arm64: dts: rp1: Add support for RaspberryPi's RP1 deviceAndrea della Porta
RaspberryPi RP1 is a multi function PCI endpoint device that exposes several subperipherals via PCI BAR. Add a dtb overlay that will be compiled into a binary blob and linked in the RP1 driver. This overlay offers just minimal support to represent the RP1 device itself, the sub-peripherals will be added by future patches. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-6-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09ARM64: dts: bcm63158: Add BCMBCA peripheralsLinus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA blocks for the BCM63158 based on the vendor files 63158_map_part.h and 63158_intr.h from the "bcmopen-consumer" code drop. The DTSI file has clearly been authored for the B0 revision of the SoC: there is an earlier A0 version, but this has the UARTs in the legacy PERF memory space, while the B0 has opened a new peripheral window at 0xff812000 for the three UARTs. It also has a designated AHB peripheral area at 0xff810000 where the DMA resides, the peripheral range window fits these two peripheral groups. This SoC has up to 256 possible GPIOs due to having 8 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-12-86f97ab4326f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09ARM64: dts: bcm6858: Add BCMBCA peripheralsLinus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. ARM64 SoCs have additional peripherals at 0xff858000. Extend the peripheral window range to 0x400000 and add the DMA controller at offset 0x59000. Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA blocks for the BCM6858 based on the vendor files 6858_map_part.h and 6858_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 256 possible GPIOs due to having 8 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-11-86f97ab4326f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09ARM64: dts: bcm6856: Add BCMBCA peripheralsLinus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. ARM64 SoCs have additional peripherals at 0xff858000. Extend the BCM6856 the PERF window to 0x400000 and add the DMA block at offset 0x59000. Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA blocks for the BCM6856 based on the vendor files 6856_map_part.h and 6856_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 256 possible GPIOs due to having 8 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-10-86f97ab4326f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09ARM64: dts: bcm4908: Add BCMBCA peripheralsLinus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. ARM64 SoCs have additional peripherals at 0xff858000, we extend the peripheral bus range to 0x400000 to cover this area. Add the watchdog, remaining GPIO blocks, RNG, and DMA blocks for the BCM4908 based on the vendor files 4908_map_part.h and 4908_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 320 possible GPIOs due to having 10 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-9-86f97ab4326f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-05-09Merge tag 'arm-soc/for-6.16/devicetree-arm64' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM64-based SoCs Device Tree updates for 6.16, please pull the following: - Stanimir adds and enables the PCIe root complex Device Tree nodes present on the Raspberry Pi 5 - Rob updates the BCM2712 L2 cache node names to use a more comforming name * tag 'arm-soc/for-6.16/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node names arm64: dts: broadcom: bcm2712-rpi-5-b: Enable PCIe DT nodes arm64: dts: broadcom: bcm2712: Add PCIe DT nodes Link: https://lore.kernel.org/r/20250505165810.1948927-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-05arm64: dts: bcm: Add reference to RPi 2 (2nd rev)Stefan Wahren
This adds a reference to the dts of the Raspberry Pi 2 (2nd rev), so we don't need to maintain the content in arm64. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20250418143307.59235-4-wahrenst@gmx.net Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-04-11arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node namesRob Herring (Arm)
There's no need include the CPU number in the L2 cache node names as the names are local to the CPU nodes. The documented node name is also just "l2-cache". Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/all/20250410-dt-cpu-schema-v2-2-63d7dc9ddd0a@kernel.org/ Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-09 11:13:23 +0000