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spear13xx.dtsi defines a thermal_flags property in spear thermal sensor
node which is both unused in kernel and undocumented in spear thermal
sensor's binding.
There were no dtbs_check warnings associated with this property as the
underlying spear thermal binding was not converted to DTSchema.
Most likely st,thermal-flags is a misspelling of thermal_flags in
spear13xx.dtsi. Since both st/spear1310.dtsi and st/spear1340.dtsi
define st,thermal-flags property in spear thermal sensor node, we can
safely remove this property from spear13xx.dtsi.
Signed-off-by: Gopi Krishna Menon <krishnagopi487@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20260329123449.309814-3-krishnagopi487@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Since the ETZPC system bus was introduced, misalignments have appeared
in some nodes moved under the etzpc parent node.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20260304-mp1x_alignment_issues-v1-2-19a8013782a5@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Since the ETZPC system bus was introduced, misalignments have appeared
in some nodes moved under the etzpc parent node.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20260304-mp1x_alignment_issues-v1-1-19a8013782a5@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Since DMA resources are limited, remove the DMA related properties
of i2c2 and i2c5 in stm32mp157c-ev1.dts.
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/20260224-stm32-i2c-dt-updates-v1-3-347cf6fca7d1@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Update all i2c nodes with the following properties:
- replace interrupts with interrupts-extended and rely on exti
- add the wakeup-source property
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/20260224-stm32-i2c-dt-updates-v1-2-347cf6fca7d1@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Update all i2c nodes with the following properties:
- replace interrupts with interrupts-extended and rely on exti
- add dma properties
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/20260224-stm32-i2c-dt-updates-v1-1-347cf6fca7d1@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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The following DTOs are supported on STM32MP15xx DHCOM PDK2:
- DH 460-200 SRAM board in header X11
- DH 497-200 adapter card with EDT ETM0700G0EDH6 Parallel RGB panel
- DH 505-200 adapter card with Chefree CH101OLHLWH-002 LVDS panel
- DH 531-100 SPI/I2C board in header X21
- DH 531-200 SPI/I2C board in header X22
- DH 560-200 7" LCD board in header X12
- DH 638-100 mezzanine card with RPi 7" DSI panel attached on top
- DH 672-100 expansion card, which contains CAN/FD transceiver and
enables PDK2 to use one more CAN/FD interface
The following DTOs are supported on STM32MP15xx DHCOM DRC02:
- Enable configuration where the DHSOM inserted into the DRC02 has
RSI 9116 WiFi populated on the SoM and where the microSD slot on
the bottom of DRC02 must not be used.
This permits a non-default configuration of the SoM and DRC02 board
used for custom device setup with on-SoM WiFi.
The following DTOs are supported on STM32MP15xx DHCOM PicoITX:
- DH 548-200 adapter card with Multi-Inno MI0700D4T-6 7" DPI panel
- DH 553-100 adapter card with Team Source Display TST043015CMHX 4.3" DPI panel
- DH 626-100 adapter card with Chefree CH101OLHLWH-002 LVDS panel
The following DTOs are supported on STM32MP15xx DHCOR Avenger96:
- FDCAN1 on low-speed expansion X6
- FDCAN2 on low-speed expansion X6
- AT24C04 I2C EEPROM on low-speed expansion X6 I2C1
- AT24C04 I2C EEPROM on low-speed expansion X6 I2C2
- AT25AA010A SPI EEPROM on low-speed expansion X6 SPI2
- 96boards OV5640 mezzanine card with sensor connected to port J3.
- DH 644-100 mezzanine card with Orisetech OTM8009A DSI panel
- DH 644-100 mezzanine card with RPi 7" DSI panel
The following DTOs are supported on STM32MP13xx DHCOR DHSBC:
- joy-IT RB-TFT3.2-V2 240x320 SPI LCD and XPT2046 resistive touch controller
Signed-off-by: Marek Vasut <marex@nabladev.com>
Link: https://lore.kernel.org/r/20260121085347.10368-3-marex@nabladev.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Enable CoreSight peripherals on the stm32mp135f-dk board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20260226-debug_bus-v6-11-5d794697798d@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Enable CoreSight peripherals on the stm32mp157c-ev1 board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20260226-debug_bus-v6-10-5d794697798d@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Enable CoreSight peripherals on the stm32mp15xx-dkx boards. All boards
including this file are embedding a dual core SoC so this change is
applicable.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20260226-debug_bus-v6-9-5d794697798d@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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On stm32mp1x boards, enable the debug bus so we always try to probe
the debug peripherals, if their status and the debug configuration
allow it.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20260226-debug_bus-v6-8-5d794697798d@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Some peripherals cannot be probed if a debug configuration is not set
in the BSEC.
Introduce a debug bus that will check the debug subsystem accessibility
before probing these peripheral drivers.
Add Coresight peripheral nodes under this bus and add the appropriate
access-controllers property to the HDP node.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20260226-debug_bus-v6-7-5d794697798d@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Enable the DMA-MDMA chaining for the dcmi (camera capture)
in order to be able to achieve higher resolution.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/20260106-stm32-dcmi-dma-chaining-v2-12-70688bccd80a@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Introduce the sram node in order to be used by drivers
requiring SRAM memory space.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/20260106-stm32-dcmi-dma-chaining-v2-11-70688bccd80a@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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- stm32mp15xx-phycore-som: add NAND device on FMC interface to support
the SoM version equipped with NAND flash instead of eMMC.
- stm32mp15xx-phyboard-sargas: define pinctrl for PWM5, LTDC and DCMI
interfaces used on phyBOARD-Sargas. Those interfaces are not enabled by
default as PHYTEC displays and PHYTEC cameras are enabled and configured
throught device tree overlays.
PWM5 is used for LCD backlight command.
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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- Remove "stm32-pinfunc.h" include as it is already include in
"stm32mp15-pinctrl.dtsi" file.
- reserved-memory: reorder the memory sections (lower to higher
addresses).
- Move vendor properties (go last).
- Remove useless compatible values:
- QSPI flash: remove the winbond compatible. jedec is enought as the
NOR flahses are detectable.
- EEPROM: "atmel,24c32" is enought.
- Use uppercase for regulator-name properties.
- In pmic node: use the names from the PHYTEC SoM schematics.
- stmpe811 touch: fix dts schema to comply with st,stmpe.yaml.
- Fix one "multiple blank lines" detected by checkpatch.
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Following peripherals are optional on phyCORE-STM32MP15x following
PHYTEC standard SoM variants: external RTC, EEPROM, SPI NOR.
Also NAND (fmc) can be populated instead of eMMC (sdmmc2).
So disable those peripherals on SoM dtsi file and enable them on board
dts file.
Additionally, enable by default the "DTS" SoC IP on common SoM dtsi file
as it is not an optional IP in STM32MP15x SoC.
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Link: https://lore.kernel.org/r/20251210101611.27008-10-c.parant@phytec.fr
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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aliases are common to every phyboard-sargas version. So move it to
the common phyboard dtsi file.
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Link: https://lore.kernel.org/r/20251210101611.27008-9-c.parant@phytec.fr
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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"memory" node is not necessary as the bootloader is taking care of
passing the correct DDR size.
However keep a dummy memory node with the minimum DDR size (512MB) with
comment explaining that.
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Link: https://lore.kernel.org/r/20251210101611.27008-8-c.parant@phytec.fr
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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- Add missing chip select pin group in pinctrl.
- Overwrite the memory map to the Flash device size (16MB) is necessary
to avoid waste of virtual memory that will not be used.
Without this modification, qspi probe fails because of ioremap error.
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Link: https://lore.kernel.org/r/20251210101611.27008-7-c.parant@phytec.fr
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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- UART4:
"uart4_pins_a" pinmux option does not apply here, as PB9 should be
used for UART4_TX instead of PG11 (PG11 is LCD_B3 on Sargas).
Use "uart4_pins_f" instead.
Also remove "pinctrl-3" which is useless (identical to "pinctrl-1").
- SAI2 A:
"sai2a_pins_b" pinmux option does not apply here, as only PI6 is used
for SAI2 A ("SAI2_SD_A"). Other pins of this group (PI7 and PD13) are
not used for audio.
Use "sai2a_sleep_pins_d" instead.
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Link: https://lore.kernel.org/r/20251210101611.27008-6-c.parant@phytec.fr
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add add alternate pinmux for following interfaces used on
phyBOARD-Sargas:
- UART4
- LTDC
- DCMI
- TIM5
- SAI2
Fix "ethernet0_rgmii_pins_d" pinmux used on phyCORE-STM32MP15x:
ETH_RGMII_GTX_CLK pin was missing.
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Link: https://lore.kernel.org/r/20251210101611.27008-5-c.parant@phytec.fr
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add stm32mp15xx-phycore-som.dtsi device tree file to split hardware
features between the phyBOARD (baseboard) and the phyCORE (SoM).
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Link: https://lore.kernel.org/r/20251210101611.27008-3-c.parant@phytec.fr
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Rename "stm32mp157c-phycore-*" device tree for the following reasons:
- The name of the dts should match to the phyBOARD name and not the name
of the SoM ("phycore-stm32mp1-3" was initialy coming from the name of
the yocto machine from meta-phytec).
- PHYTEC manages different SoM configurations with different STM32MP15x
SoC versions, so common dtsi files starting with "stm32mp15xx-*" should
be used (as it is done for ST boards for example).
- Add "-rdk" as suffix (for "Rapid Development Kit") to match our others
phytec boards dts names (imx6, imx6ul,..).
- "model" property is updated to introduce the name "phyBOARD-Sargas".
Signed-off-by: Christophe Parant <c.parant@phytec.fr>
Link: https://lore.kernel.org/r/20251210101611.27008-2-c.parant@phytec.fr
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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These .dtsi files are not included anywhere in the tree and can't be
tested.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20260113201340.36950-1-robh@kernel.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add the sleep state of the spi1 instance on stm32mp157c-ev1.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/20251218-stm32-spi-enhancements-v2-4-3b69901ca9fe@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add options/u-boot/boot-led property to specify to U-Boot
the LED which indicates a successful boot.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-10-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-11-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-12-50a3a9b339a8@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add options/u-boot/boot-led property to specify to U-Boot
the LED which indicates a successful boot.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-1-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-2-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-3-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-4-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-5-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-6-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-7-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-8-50a3a9b339a8@foss.st.com
Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-9-50a3a9b339a8@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add led-red node for stm32mp15xx-dkx, this LED is used as status
LED in U-Boot.
Update led-blue node by adding color property and replacing obsolete
label property by function property.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-13-45090db9e2e5@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add led-red node for stm32mp157c-ed1.
This LED is used as status LED in U-Boot.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-12-45090db9e2e5@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add LED red node for stm32mp135f-dk.
This LED is used as status lLED in U-Boot.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-11-45090db9e2e5@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add green and red LEDs support for stm32h743-eval.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-9-45090db9e2e5@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add gpio led support for LED green,orange,red and blue
in stm32h743i-disco.dts.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-8-45090db9e2e5@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add function porperty for led nodes.
Add LED color property for LED nodes.
Reorder include dt-bindings.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-2-45090db9e2e5@foss.st.com
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-3-45090db9e2e5@foss.st.com
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-4-45090db9e2e5@foss.st.com
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-5-45090db9e2e5@foss.st.com
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-6-45090db9e2e5@foss.st.com
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-7-45090db9e2e5@foss.st.com
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-10-45090db9e2e5@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Reorder nodes by alphabetical order.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-1-45090db9e2e5@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Pull SoC devicetree updates from Arnd Bergmann:
"Three new SoCs got added in existing arm64 chip families:
- Renesas R-Car X5H (R8A78000) is a new generation of automotive
SoCs, based on 16 Cortex-A720 (Armv9.2) cores, which makes the the
currently highest-perforance embedded SoC.
- TI AM62L is a new variant of the AM62 family of industrial SoCs,
this one comes without a GPU.
- Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip
based on Cortex-A53, and closely related to MSM8917 (Snapdragn
425), which we already support.
In addition, there are a good number of newly supported machines
across SoC families:
- Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers
- Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124,
Qualcomm MSM8937 and Qualcomm MSM8939,
- Two Laptops based on Qualcomm SoCs: one using the older sdm850, the
other using x1p42100.
- One Router based on Rockchips RK3568
- 24 variants of the Enclustra Mercury system-on-module, all based on
32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit
SocFPGA Agilex chips..
- 30 industrial/embedded boards and single-board computers, using
various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm,
Spacemit, and Starfive.
In total there are 783 commits here, the majority of these improving
hardware support and cleaning up devicetree files across the tree,
with the majority of the changes going into the Qualcomm, NXP, Renesas
and Rockchips platforms"
* tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (782 commits)
arm64: dts: mediatek: mt8195: Fix address range for JPEG decoder core 1
ARM: dts: samsung: exynos4412-midas: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-trats: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-i9100: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: universal_c210: turn off SDIO WLAN chip during system suspend
arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs
arm64: dts: Add gpio_intc node for Amlogic S7D SoCs
arm64: dts: Add gpio_intc node for Amlogic S7 SoCs
arm64: dts: Add gpio_intc node for Amlogic S6 SoCs
arm64: dts: amlogic: s7d: add ao secure node
arm64: dts: amlogic: s7: add ao secure node
arm64: dts: amlogic: s6: add ao secure node
arm64: dts: amlogic: Fix the register name of the 'DBI' region
dts: arm64: amlogic: add a5 pinctrl node
arm64: dts: amlogic: s7d: add power domain controller node
arm64: dts: amlogic: s7: add power domain controller node
arm64: dts: amlogic: s6: add power domain controller node
dts: arm64: amlogic: Add ISP related nodes for C3
arm64: dts: meson: add initial device-tree for Tanix TX9 Pro
dt-bindings: arm: amlogic: add support for Tanix TX9 Pro
...
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Add the interrupt line that can be used for the early interrupt of
the IWDG2 to the IWDG2 node
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20251031-iwdg1-v2-4-2dc6e0116725@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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On the stm32mp135f-dk board, the IWDG1 is secured and used to monitor
the cortex-A7. Use the ARM SMC watchdog to communicate with it.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20251031-iwdg1-v2-3-2dc6e0116725@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add the arm_wdt node in the stm32mp131.dtsi SoC device tree file. When
the platform watchdog is managed by the secure world, SMC calls are used
to interact with it.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20251031-iwdg1-v2-2-2dc6e0116725@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add the IWDG1 node in the stm32mp131.dtsi SoC device tree file. It can
be used by Linux as the Cortex-A7 watchdog when it's configured as
non-secure.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20251031-iwdg1-v2-1-2dc6e0116725@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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The LXA device trees are the only STM32MP1 device tree that specify
vusb_d/usb_a-supply and apparently not for good reason:
- vusb_d-supply (vdd_usb) is the same as the phy-supply for usbphyc_port1
- vusb_a-supply (reg18) is the same as vdda1v8-supply for usbphyc_port1
and usbphyc_port1 is linked to the usbotg_hs node via the phys property.
Specifying the regulators in the &usbotg_hs node is thus superfluous and
has been even found to be harmful in one instance:
Linux v6.10 was found to lock up every 50-125 or so reboots on the LXA
TAC when the DWC2 driver probe enables the regulators in bulk, unless
both properties were removed.
This issue was so far not reproducible on v6.17 (> 500 reboots), but as
these properties are unnecessary and different from other STM32MP1
boards, remove them anyway.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.kernel.org/r/20251007-lxa-usb-dt-v1-1-cacde8088bb9@pengutronix.de
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Move st,adc-freq, st,mod-12b, st,ref-sel, and st,sample-time properties
from the touchscreen subnode to the parent touch@44 node. These properties
are defined in the st,stmpe.yaml schema for the parent node, not the
touchscreen subnode, resolving the validation error about unevaluated
properties.
Fixes: 27538a18a4fcc ("ARM: dts: stm32: add STM32MP1-based Phytec SoM")
Signed-off-by: Jihed Chaibi <jihed.chaibi.dev@gmail.com>
Link: https://lore.kernel.org/r/20250915224611.169980-1-jihed.chaibi.dev@gmail.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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tvout node do not need the cells fields. Remove them.
Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://patch.msgid.link/20250717-sti-rework-v1-4-46d516fb1ebb@gmail.com
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
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The display subsystem represent how IPs are interacting together and
have nothing to do within the SoC node.
Extract it from the SoC node and let IPs nodes in the Soc node.
Several nodes did not use conventional name:
* sti-display-subsystem -> display-subsystem
* sti-controller -> display-controller
* sti-tvout -> encoder
* sti-hda -> analog
* sti-hqvdp -> plane
Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://patch.msgid.link/20250717-sti-rework-v1-3-46d516fb1ebb@gmail.com
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.18, round 1
Highlights:
----------
- MPU:
- STM32MP13:
- Add missing Ethernet1/2 PTP reference clocks.
- Add Hardware debug port (HDP).
- STMP32MP15:
- Add resets property to m_can nodes.
- Add Hardware debug port (HDP) and enable it on stm32mp157c-dk2
board.
- Reserve leds for CM4 on stm32mp15xx-ed1 and stm32mp15xx-dkx.
- stm32mp151c-plyaqm:
Use correct dai-format property.
- STM32MP23:
- Add Ethernet1 MAC controller on stm32mp235f-dk board:
It is connected to a RTL8211F-CG phy through RGMII.
- Fix GPIO bank definition & memory size (DDR).
- STM32MP25:
- Add Ethernet1 MAC controller on stm32mp257f-dk board.
It is connected to a RTL8211F-CG phy through RGMII.
- Add Ethernet1 MAC controller on stm32mp257f-ev1 board.
It is connected to a RTL8211F-CG phy through RGMII.
- Add display support by enabling the following IPs on
stm32mp257f-ev1:
* LTDC
* LVDS
* WSVGA LVDS panel (1024x600)
* Panel LVDS backlight as GPIO backlight
* ILI2511 i2c touchscreen
- Add PCIe Root complex and Endpoint support on stm32mp257f-ev1.
Root complex mode is used by default.
* tag 'stm32-dt-for-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (30 commits)
arm64: dts: st: fix memory region size on stm32mp235f-dk
arm64: dts: st: remove gpioj and gpiok banks from stm32mp231
arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk
arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1
arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk
arm64: dts: st: add eth1 pins for stm32mp2x platforms
ARM: dts: stm32: add missing PTP reference clocks on stm32mp13x SoCs
arm64: dts: st: enable display support on stm32mp257f-ev1 board
arm64: dts: st: add clock-cells to syscfg node on stm32mp251
arm64: dts: st: add lvds support on stm32mp255
arm64: dts: st: add ltdc support on stm32mp255
arm64: dts: st: add ltdc support on stm32mp251
ARM: dts: stm32: add resets property to m_can nodes in the stm32mp153
dt-binding: can: m_can: add optional resets property
arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board
arm64: dts: st: Add PCIe Endpoint mode on stm32mp251
arm64: dts: st: Add PCIe Root Complex mode on stm32mp251
arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi
arm64: defconfig: Enable STMicroelectronics STM32 DMA3 support
ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp157c-dk2 board
...
Link: https://lore.kernel.org/r/13153fc2-1abe-4d53-807a-5d289981a63d@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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ETH1/2 miss their PTP reference clock in the SoC device tree. Add them
as the fallback is not correctly handled for PPS generation and it seems
there's no reason to not add them.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20250901-relative_flex_pps-v4-3-b874971dfe85@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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On the STM32MP153 the m_cam IP cores (a.k.a. FDCAN) have an external
shared reset in the RCC. Add the reset to both m_can nodes.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20250807-stm32mp15-m_can-add-reset-v2-2-f69ebbfced1f@pengutronix.de
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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On the stm32mp157fc-dk2 board, we can observe the hdp GPOVAL function on
SoC pin E13 accessible on the pin 5 on the Arduino connector CN13.
Add the relevant configuration but keep it disabled as it's used for
debug only.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-8-faeecf7aaee1@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Introduce hdp node to output a user defined value on port hdp2.
Add pinctrl nodes to be able to output this signal on one SoC pin.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-7-faeecf7aaee1@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into soc/dt
STi dt fixes:
- Remove unused stih407-clock.dtsi file
* tag 'sti-dt-for-v6.18-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
ARM: dts: sti: remove dangling stih407-clock file
Link: https://lore.kernel.org/r/4a710c05-aeeb-4421-b3a1-5bfb8230d51d@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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