summaryrefslogtreecommitdiff
path: root/Documentation/devicetree
AgeCommit message (Collapse)Author
2026-02-25dt-bindings: usb: ti,dwc3: convert to DT schemaCharan Pedumuru
Convert OMAP DWC3 USB Glue Layer binding to DT schema. Changes made during the conversion: - Drop the ti,hwmods property, as it is not used by any in-tree DTS files. Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260127-ti-usb-v2-2-9dd6a65b43df@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-02-25dt-bindings: usb: ti,omap4-musb: convert to DT schemaCharan Pedumuru
Convert OMAP MUSB USB OTG Controller binding to DT schema. Changes during conversion: - Include "interrupts" and "interrupt-names" properties in the YAML, as they are used by many in-tree DTS files. - Extend the "power" property to allow the value 150 (in addition to existing values), since this is present in several in-tree DTS examples. - Drop the ti,hwmods property, as it is not used by any in-tree DTS files. Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260127-ti-usb-v2-1-9dd6a65b43df@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-02-25dt-bindings: mtd: mxc-nand: add i.MX25 and i.MX27 nand supportFrank Li
Add compatible string fsl,imx25-nand and fsl,imx27-nand (over 15 years chips). Add one optional clocks for it because i.MX25 and i.MX27 upstream DTS defines them. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-02-25dt-bindings: mtd: Describe MTD partitions concatenationAmit Kumar Mahapatra
The AMD QSPI controller supports an advanced connection modes called Stacked mode which allow the controller to treat two different flashes as one storage. In Stacked connection mode flashes share the same SPI bus, but different CS line, controller driver asserts the CS of the flash to which it needs to communicate. Stacked mode is a software abstraction rather than a controller feature or capability. At any given time, the controller communicates with one of the two connected flash devices, as determined by the requested address and data length. If an operation starts on one flash and ends on the other, the mtd layer needs to split it into two separate operations and adjust the data length accordingly. For more information on the modes please feel free to go through the controller flash interface below [1]. To support stacked mode, the existing MTD concat driver has been extended to be more generic, enabling multiple sets of MTD partitions to be virtually concatenated, with each set forming a distinct logical MTD device. A new Device Tree property is introduced to facilitate this, containing phandles of the partitions to be concatenated with the one where the property is defined. This approach supports multiple sets of concatenated partitions. [1] https://docs.amd.com/r/en-US/am011-versal-acap-trm/QSPI-Flash-Device-Interface Suggested-by: Miquel Raynal <miquel.raynal@bootlin.com> Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-02-25dt-bindings: arm: qcom: Add ASUS Vivobook X1P42100 variantJens Glathe
The ASUS Vivobook S15 (S5507) [1] is available with Hamoa and Purwa SoC. Add the Purwa-based variant: asus,vivobook-s15-x1p4 compatible to Purwa SoC [1]: https://www.asus.com/de/laptops/for-home/vivobook/asus-vivobook-s-15-s5507/techspec/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Link: https://lore.kernel.org/r/20260214-b4-vivobook-v3-1-3c88065bbf77@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-25dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent propertyKhairul Anuar Romli
The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller operates on a cache-coherent AXI interface, where DMA transactions are automatically kept coherent with the CPU caches. In previous generations SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there is no need for dma-coherent property to be presence. In Agilex 5, the architecture has changed. It introduced a coherent interconnect that supports cache-coherent DMA. Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://patch.msgid.link/20260131172856.29227-1-dinguyen@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-25dt-bindings: dma: rz-dmac: Document RZ/G3L SoCBiju Das
Document the Renesas RZ/G3L DMAC block. This is identical to the one found on the RZ/G3S SoC. Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260203103031.247435-2-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-02-24dt-bindings: arm: qcom: add Dragonboard 820c using APQ8096SG SoCDmitry Baryshkov
There exists a variant of the DB820c board, using the APQ8096SG (MSM8996 Pro) SoC. Describe it in the bindings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20251111-db820c-pro-v1-1-6eece16c5c23@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-24docs: dt: unittest: update to current unittest filenamesMarkus Heidelberg
There have been several renamings and modified Make rules since introduction of this unittest document. The file list in the Chinese translation had been extended. For a change to drivers/of/unittest-data/tests-*.dtsi surrounding translation has to be updated. Signed-off-by: Markus Heidelberg <m.heidelberg@cab.de> Link: https://patch.msgid.link/20260223111207.54640-1-m.heidelberg@cab.de Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-02-24dt-bindings: arm: cpus: Deprecate Qualcomm generic compatiblesKrzysztof Kozlowski
Move compatibles for Qualcomm Kryo and Oryon custom CPU cores out of the enum into separate one with deprecated: true annotation, because these are too generic names. These are names of the families and there are significant differences within individual processors, e.g. Kryo6xx can based on architectures from Cortex-X2, A710, A510 to A78 and probably more. Just like other vendor processors are differentiated, also Qualcomm CPUs should come with specific compatibles. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Konrad Dybcio <konradybcio@kernel.org> Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://patch.msgid.link/20260223074422.18468-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-02-24dt-bindings: arm: fsl: Add i.MX93 Wireless EVK boardSherry Sun
Add DT compatible string for NXP i.MX93 Wireless EVK board. i.MX93 Wireless SiP is created by integrating i.MX93 and IW610 WLCSP (Wi-Fi + BLE + 802.15.4). And i.MX93 Wireless EVK board with the i.MX93 Wireless SiP basically reuse the i.MX93 11x11 EVK board, with some minor functional and pin connection differences. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-02-24dt-bindings: arm: fsl: add Variscite DART-MX95 BoardsStefano Radaelli
Add DT compatible strings for Variscite DART-MX95 SoM and Variscite development carrier Board. Link: https://variscite.com/system-on-module-som/i-mx-9/dart-mx95/ Link: https://variscite.com/carrier-boards/sonata-board/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-02-24dt-bindings: soc: imx93-media-blk-ctrl: Add PDFC subnode to schema and exampleLiu Ying
i.MX93 SoC mediamix blk-ctrl contains one DISPLAY_MUX register which configures parallel display format by using the "PARALLEL_DISP_FORMAT" field. Document the Parallel Display Format Configuration(PDFC) subnode and add the subnode to example. [m.felsch@pengutronix.de: add bus-width] Signed-off-by: Liu Ying <victor.liu@nxp.com> [m.felsch@pengutronix.de: port to v6.18-rc1] Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-02-24spi: dt-bindings: snps,dw-abp-ssi: Remove unused bindingsAndy Shevchenko
As stated in the da0a672268b3 ("spi: dw: Remove not-going-to-be-supported code for Baikal SoC") the Baikal platforms are not supported and the respective driver code was removed. Remove the currently unused bindings. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260224115218.3499222-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-02-24ata: ahci-dwc: Remove not-going-to-be-supported code for Baikal SoCAndy Shevchenko
As noticed in the discussion [1] the Baikal SoC and platforms are not going to be finalized, hence remove stale code. Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2026-02-24dt-bindings: arm: axis: Add ARTPEC-9 alfred boardRavi Patel
Document the Axis ARTPEC-9 SoC binding and the alfred board which uses ARTPEC-9 SoC. Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251119131302.79088-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-24dt-bindings: clock: Add ARTPEC-9 clock controllerGyoungBo Min
Add dt-schema for Axis ARTPEC-9 SoC clock controller. The Clock Management Unit (CMU) has a top-level block CMU_CMU which generates clocks for other blocks. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS0 - CMU_FSYS1 - CMU_IMEM - CMU_PERI Signed-off-by: GyoungBo Min <mingyoungbo@coasia.com> Reviewed-by: Kyunghwan Kim <kenkim@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251029130731.51305-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-24dt-bindings: mmc: rockchip-dw-mshc: Add RV1103B compatibleFabio Estevam
The RV1103B uses the DesignWare MSHC controller compatible with the existing Rockchip RK3288 variant. Add the rockchip,rv1103b-dw-mshc compatible string. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-24dt-bindings: mmc: arasan,sdhci: Add Axiado AX3000 SoCSriNavmani A
Add compatible strings for Axiado AX3000 SoC eMMC controller which is based on Arasan eMMC controller. Signed-off-by: SriNavmani A <srinavmani@axiado.com> Signed-off-by: Tzu-Hao Wei <twei@axiado.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-24dt-bindings: pinctrl: imx35: add compatible string fsl,imx25-iomuxcFrank Li
Add compatible string fsl,imx25-iomuxc. Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-02-24dt-bindings: pinctrl: convert fsl,imx27-pinctrl.txt to YAMLFrank Li
Convert fsl,imx27-pinctrl.txt to YAML format. Additional changes: - Add the compatible string "fsl,imx1-iomuxc". - Add gpio@... child nodes. - Add ranges property. - Remove the redundant intermediate node between pinmux and group nodes. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-02-24dt-bindings: pinctrl: document the Eliza Top Level Mode MultiplexerAbel Vesa
Document the Top Level Mode Multiplexer on the Eliza Platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-02-23Merge branch 'ib-iio-thermal-qcom-pmic5' into togregJonathan Cameron
Immutable branch to allow this base work to be merged into thermal.
2026-02-23dt-bindings: iio: amplifiers: Add AD8366 supportRodrigo Alencar
Add device tree binding documentation for amplifiers and digital attenuators. This covers different device variants with similar SPI control. Each device has its own gain range and step, hence no fallback compatibles are used. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2026-02-23dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADCJishnu Prakash
For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs going through PBS(Programmable Boot Sequence) firmware through a single register interface. This interface is implemented on SDAM (Shared Direct Access Memory) peripherals on the master PMIC PMK8550 rather than a dedicated ADC peripheral. Add documentation for PMIC5 Gen3 ADC and update SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode. Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2026-02-23dt-bindings: iio: adc: Split out QCOM VADC channel propertiesJishnu Prakash
Split out the common channel properties for QCOM VADC devices into a separate file so that it can be included as a reference for devices using them. This will be needed for the upcoming ADC5 Gen3 binding support patch, as ADC5 Gen3 also uses all of these common properties. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2026-02-23dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8940Barnabás Czémán
Add the compatible for MSS as found on the MSM8940 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20260107-mss-v4-8-9f4780345b6f@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8937Barnabás Czémán
Add the compatible for MSS as found on the MSM8937 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20260107-mss-v4-6-9f4780345b6f@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8917Barnabás Czémán
Add the compatible for MSS as found on the MSM8917 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20260107-mss-v4-4-9f4780345b6f@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MDM9607Barnabás Czémán
Add the compatible for MSS as found on the MDM9607 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20260107-mss-v4-2-9f4780345b6f@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: fsl: add compatible string fsl,imx25-aipsFrank Li
Add compatible string fsl,imx25-aips to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb: /soc/bus@43f00000/bridge@43f00000: failed to match any schema with compatible: ['fsl,imx25-aips'] Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://patch.msgid.link/20260211221529.3745404-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-02-23dt-bindings: clock: qcom: Add video clock controller on Glymur SoCTaniya Das
Add compatible string for Glymur video clock controller and the bindings for Glymur Qualcomm SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-2-8f7d8b4d8edd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: clock: qcom: document the Glymur GPU Clock ControllerTaniya Das
Glymur SoC has Qualcomm GX(graphics) clock controller and also the Graphics clock controller. The GX graphics clock controller helps in the recovery of the Graphics subsystem. Add bindings documentation for the Glymur Graphics Clock and Graphics power domain Controller for Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260127-glymur_gpucc-v1-1-547334c81ba2@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: soc: qcom: qcom,pmic-glink: Add Glymur and Kaanapali compatiblesAnjelique Melendez
Glymur (a recent compute platform) and Kaanapali (a recent mobile platform) have the charger FW running on a new subsystem SOCCP (SOC Control Processor) instead of on ADSP like in previous platforms. Because of this, pmic_glink interface on Glymur and Kaanapali platforms are not compatible with previous platforms. Hence, add new compatible strings for Glymur and Kaanapali. Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260209204915.1983997-2-anjelique.melendez@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: clock: qcom,glymur-dispcc: De-acronymize SoC nameKrzysztof Kozlowski
Glymur is a codename of Qualcomm SoC, not an acronym. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260217130047.281813-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23dt-bindings: arm: qcom: Document Glymur SoC and boardPankaj Patil
Document Glymur SoC bindings and Compute Reference Device (CRD) board id Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260219-upstream_v3_glymur_introduction-v8-1-8ce4e489ebb6@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-02-23spi: dt-bindings: renesas,rzv2h-rspi: allow multiple DMAsCosmin Tanislav
All supported SoCs have multiple DMA controllers that can be used with the RSPI peripheral. The current bindings only allow a single pair of RX and TX DMAs. The DMA core allows specifying multiple DMAs with the same name, and it will pick the first available one. There is an exception in the base dt-schema rules specifically for allowing this behavior (dtschema/schemas/dma/dma.yaml). dma-names: anyOf: - uniqueItems: true - items: # Hack around Renesas bindings which repeat entries to support # multiple possible DMA providers enum: [rx, tx] Allow multiple DMAs to have the same name and only restrict the possible names of the DMA channels, not their count. For RZ/T2H and RZ/N2H SoCs, limit the number of DMA channels to 6, as they have 3 DMA controllers. For RZ/V2H and RZ/V2N SoCs, limit the number of DMA channels to 10, as they have 5 DMA controllers. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-02-23dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controllerAlbert Yang
Add device tree bindings for the Black Sesame Technologies DWCMSHC SDHCI controller used in C1200 SoC. The binding describes a Synopsys DesignWare Cores Mobile Storage Host Controller with BST-specific extensions including: - Two register regions (core SDHCI and CRM registers) - Optional memory-region for bounce buffer support - Fixed clock input Signed-off-by: Ge Gordon <gordon.ge@bst.ai> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: spacemit,sdhci: add support for K3 SoCYixun Lan
The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1 generation, while fixed the broken 64BIT DMA issue. Introduce a compatible string to enable support for it. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: arm,pl18x: Do not use plural form of a proper noun PrimeCellVladimir Zapolskiy
As a proper noun PrimeCell is a single entity and it can not have a plural form, fix the typo. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: spacemit,sdhci: add reset supportYixun Lan
The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus which shared by all controllers, while another one connect to individual controller separately. Signed-off-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: arasan,sdhci: Allow "dma-coherent" propertyRob Herring (Arm)
The Arasan SDHCI controller is DMA coherent on the APM merlin SoC, so allow the dma-coherent property. No reason implementations can't also be coherent and there's not an SoC specific compatible, so allow it on any platform. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: brcm,iproc-sdhci: Allow "dma-coherent" and "iommus" propertiesRob Herring (Arm)
The Broadcom iProc SDHCI controller is DMA coherent and/or behind an IOMMU on some Broadcom SoCs, so allow the dma-coherent and iommus properties. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: cdns,sdhci: Drop required "resets" on AMD Pensando ELBARob Herring (Arm)
The AMD Pensando ELBA DT defines no reset for the SDHCI, so it is obviously not required. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: mmc: mtk-sd: Add support for MT8189 SoCLouis-Alexis Eyraud
Add a new compatible for MMC IP in MT8189 SoC. Even though this is partially compatible with the one found in MT8196 SoC, the MT8189 SoC register layout has some slight differences and additional features. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: power: Add MediaTek MT8189 power domainIrving-CH Lin
Add dt schema and IDs for the power domain of MediaTek MT8189 SoC. The MT8189 power domain IP provide power domains control function for subsys (eg. MFG, audio, venc/vdec ...). Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23dt-bindings: power: mt8196-gpufreq: Describe nvmem provider abilityNicolas Frattaroli
On the MediaTek MT8196 SoC, the Mali GPU's "shader_present" hardware register may also include a non-functional shader core, along with the present shader cores. An efuse elsewhere in the SoC provides the shader_present mask with the fused off core omitted. However, the efuse address is not publicly disclosed. What is known though is that the GPUEB MCU reads this efuse, and exposes its contents in the memory it shares with the application processor. We can therefore describe the mediatek,mt8196-gpufreq device as being an nvmem provider for this purpose, as it does provide nvmem access in an indirect way. The shader-present child node is left out of the list of required properties as we may one day be able to describe the actual efuse region this value comes from, so the gpufreq device isn't necessarily the only device that can provide this cell, and implementations shouldn't need to implement this functionality once this is the case. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23Merge drm/drm-next into drm-misc-nextMaxime Ripard
Let's merge 7.0-rc1 to start the new drm-misc-next window Signed-off-by: Maxime Ripard <mripard@kernel.org>
2026-02-23dt-bindings: pinctrl: qcom,sm8450-lpass-lpi-pinctrl: Add SA8775P and QCS8300 ↵Mohammad Rafi Shaik
pinctrl Document compatible for Qualcomm SA8775P and QCS8300 SoC LPASS TLMM pin controller, fully compatible with previous SM8450 generation (same amount of pins and functions). Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-02-23dt-bindings: pinctrl: rockchip: Add RV1103B compatibleFabio Estevam
Document the compatible string for the RV1103B SoC. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-09 07:14:15 +0000