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2026-03-07dt-bindings: arm: atmel,at91sam9260-pit: convert to DT schemaAkhila YS
Convert Atmel Periodic interval timer (PIT) binding to YAML format. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Akhila YS <akhilayalmati@gmail.com> Link: https://lore.kernel.org/r/20260227-arm-microchip-v4-2-7e2ae1c5b5d6@gmail.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-03-07dt-bindings: arm: microchip,sama7g5-chipid : convert to DT schemaAkhila YS
Convert Atmel system registers binding to YAML format. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Akhila YS <akhilayalmati@gmail.com> Link: https://lore.kernel.org/r/20260227-arm-microchip-v4-1-7e2ae1c5b5d6@gmail.com [claudiu.beznea: alphanumerically sort the enum entries] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-03-07dt-bindings: powerpc: Add Freescale/NXP MPC83xx SoCsJ. Neuschäfer
Add a new binding for MPC83xx platforms, describing the board compatible strings used in currently existing device trees. Note that the SoC bus is called immr@... in many existing devicetrees, but this contradicts the simple-bus binding. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: J. Neuschäfer <j.ne@posteo.net> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260303-ppcyaml-soc-v5-1-2982d5a857bc@posteo.net
2026-03-07dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICEAbel Vesa
Document the Inline Crypto Engine (ICE) on the Eliza platform. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2026-03-06Merge tag 'sound-7.0-rc3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound fixes from Takashi Iwai: "Again a collection of device-specific fixes. Most of changes are fairly small device-specific quirks of fixes for HD- and USB-audio, ASoC Intel, AMD, fsl, Cirrus and co. The only large LOC is for plumbing ASoC ACP driver to add the Cirrus Logic codec support, so this one is also just adding some tables" * tag 'sound-7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (21 commits) ALSA: us122l: drop redundant interface references ASoC: amd: yc: Add DMI quirk for ASUS EXPERTBOOK PM1503CDA ASoC: dt-bindings: renesas,rz-ssi: Document RZ/G3L SoC ASoC: SDCA: Add allocation failure check for Entity name ALSA: hda/senary: Ensure EAPD is enabled during init ALSA: hda/senary: Use codec->core.afg for GPIO access ALSA: doc: usb-audio: Add doc for QUIRK_FLAG_SKIP_IFACE_SETUP ASoC: dt-bindings: tegra: Add compatible for Tegra238 sound card ALSA: hda/hdmi: Add Tegra238 HDA codec device ID ASoC: cs35l56: Suppress pointless warning about number of GPIO pulls ASoC: amd: acp: Add ACP6.3 match entries for Cirrus Logic parts ASoC: Intel: sof_sdw: Add quirk for Alienware Area 51 (2025) 0CCD SKU ASoC: rt1321: fix DMIC ch2/3 mask issue ASoC: cs35l56: Only patch ASP registers if the DAI is part of a DAIlink ASoC: fsl_easrc: Fix event generation in fsl_easrc_iec958_set_reg() ASoC: fsl_easrc: Fix event generation in fsl_easrc_iec958_put_bits() ALSA: firewire: dice: Fix printf warning with W=1 ALSA: hda/tas2781: A workaround solution to lower-vol issue among lower calibrated-impedance micro-speaker on TAS2781 ALSA: hda/realtek: Add quirk for HP Pavilion 15-eh1xxx to enable mute LED ALSA: usb-audio: Add iface reset and delay quirk for AB13X USB Audio ...
2026-03-06Merge branch 'icc-qcs8300' into icc-nextGeorgi Djakov
This series enables QoS configuration for QNOC type device which can be found on QCS8300 platform. It enables QoS configuration for master ports with predefined priority and urgency forwarding. This helps in prioritizing the traffic originating from different interconnect masters at NOC (Network On Chip). The system may function normally without this feature. However, enabling QoS helps optimize latency and bandwidth across subsystems like CPU, GPU, and multimedia engines, which becomes important in high-throughput scenarios. This is a feature aimed at performance enhancement to improve system performance under concurrent workloads. * icc-qcs8300 dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoS interconnect: qcom: qcs8300: enable QoS configuration Link: https://msgid.link/20260127090116.1438780-1-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoCBiju Das
Document RZ/G3L (R9A08G046) SYSC bindings. The SYSC block found on the RZ/G3L SoC is similar to the one found on RZ/G3S. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-06dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and ↵Biju Das
Carrier-II EVK Document Renesas RZ/G3L (R9A08G046) SoC variants and the Renesas RZ/G3L SMARC Carrier-II EVK board which is based on the Renesas RZ/G3L SMARC SoM. The RZ/G3L SMARC Carrier-II EVK consists of an RZ/G3L SoM module and a SMARC Carrier-II carrier board. The SoM module sits on top of the carrier board. Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-06Merge branch 'icc-mahua' into icc-nextGeorgi Djakov
Mahua is a derivative of the Glymur SoC and shares a significant portion of its interconnect topology with Glymur. As such, this series extends the existing Glymur interconnect driver to support Mahua, reusing common definitions where possible and adding SoC-specific configurations where necessary. * icc-mahua dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC interconnect: qcom: glymur: Add Mahua SoC support Link: https://msgid.link/20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06Merge branch 'icc-eliza' into icc-nextGeorgi Djakov
Add interconnect support for the Qualcomm Eliza SoC. * icc-eliza dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Eliza SoC interconnect: qcom: Add Eliza interconnect provider driver dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatible Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in ↵Odelu Kukatla
Eliza SoC Document the RPMh Network-On-Chip Interconnect of the Eliza platform. Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://msgid.link/20260224-eliza-interconnect-v4-1-ad75855d5018@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatibleAbel Vesa
Eliza, similarly to SM8650, uses EPSS hardware for L3 scaling. Document it. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260302-eliza-bindings-interconnect-epss-l3-v2-1-05b1848b98cc@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: qcom,glymur-rpmh: De-acronymize SoC nameKrzysztof Kozlowski
Glymur is a codename of Qualcomm SoC, not an acronym. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://msgid.link/20260217130035.281752-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatibleAaron Kling
Document the OSM L3 found in the Qualcomm SM8550 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://msgid.link/20260219-sm8550-ddr-bw-scaling-v3-1-75c19152e921@gmail.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoSOdelu Kukatla
Some QCS8300 interconnect nodes have QoS registers located inside a block whose interface is clock-gated. For those nodes, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock‑gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260127090116.1438780-2-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in ↵Raviteja Laggyshetty
Mahua SoC Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm Mahua platform. Mahua is a derivative of the Glymur SoC. Many interconnect nodes are identical and continue to use Glymur fallback compatibles. Mahua introduces SoC-specific configurations and topologies for several NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs. This updates the existing Glymur yaml schema to include Mahua-specific compatible strings, using two-cell "fallback" compatibles wherever the hardware is identical with Glymur. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260209-mahua_icc-v3-1-c65f3dfd72c8@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: arm: stm32: Modify STM32MP15x Phytec board items typesChristophe Parant
As Phytec manages different SoM configurations with different STM32MP15 SoC versions, modify the phyBOARD and SoM compatible items to "enum" instead of "const". The description concerns PHYTEC SoM equipped with STM32MP157 ("st,stm32mp157" is "const"). Also add comments in front of the enum items to be able to identify the compatible string with the phyBOARD/phyCORE names. Signed-off-by: Christophe Parant <c.parant@phytec.fr> Link: https://lore.kernel.org/r/20251210101611.27008-4-c.parant@phytec.fr Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-06dt-bindings: arm: mediatek: audsys: fix formatting issuesLouis-Alexis Eyraud
Fix indentation and drop duplicate newline to resolve the following 'make dt_binding_check' warnings: ``` ./Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:52:2: [warning] wrong indentation: expected 2 but found 1 (indentation) ./Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:84:1: [warning] too many blank lines (2 > 1) (empty-lines) ``` Fixes: a8e3d66ff5c0 ("dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant") Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2026-03-05dt-bindings: omap: Add Samsung Galaxy Tab 2 7.0 and 10.1Mithil Bavishi
Add samsung-espresso7 codename for the 7 inch variant Add samsung-espresso10 codename for the 10 inch variant Signed-off-by: Mithil Bavishi <bavishimithil@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Andreas Kemnade <andreas@kemnade.info> Link: https://patch.msgid.link/20260303203017.511-7-bavishimithil@gmail.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2026-03-05dt-bindings: display: panel-lvds: Add compatibles for Samsung LTN070NL01 and ↵Mithil Bavishi
LTN101AL03 panels The LTN070NL01 is a 7.0 inch 1024x600, 24 bit, VESA Compatible, TFT display panel The LTN101AL03 is a 10.1 inch 800x1280, 24 bit, VESA Compatible, TFT display panel Signed-off-by: Mithil Bavishi <bavishimithil@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20260303203017.511-5-bavishimithil@gmail.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2026-03-05dt-bindings: display: bridge: lvds-codec: add doestek,dtc34lm85amMithil Bavishi
Add compatible strings for the Doestek DTC34LM85AM Flat Panel Display Transmitter Signed-off-by: Mithil Bavishi <bavishimithil@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20260303203017.511-4-bavishimithil@gmail.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2026-03-05dt-bindings: vendor-prefixes: Add DoestekMithil Bavishi
Add vendor prefix for Doestek Co., Ltd. Link: http://www.doestek.co.kr/ Signed-off-by: Mithil Bavishi <bavishimithil@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://patch.msgid.link/20260303203017.511-3-bavishimithil@gmail.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2026-03-05dt-bindings: qcom,pdc: document the Eliza Power Domain ControllerAbel Vesa
Document the Power Domain Controller on the Qualcomm Eliza SoC. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260223-eliza-pdc-v1-1-fcb17464fee2@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-03-06dt-bindings: display/msm: qcom,sm8750-mdss: Fix model typoKrzysztof Kozlowski
Fix obvious model typo (SM8650->SM8750) in the description. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Fixes: 6b93840116df ("dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/707192/ Link: https://lore.kernel.org/r/20260225173419.125565-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-06dt-bindings: display: msm: Fix reg ranges and clocks on GlymurAbel Vesa
The Glymur platform has four DisplayPort controllers. The hardware supports four streams (MST) per controller. However, on Glymur the first three controllers only have two streams wired to the display subsystem, while the fourth controller operates in single-stream mode. Add a dedicated clause for the Glymur compatible to require the register ranges for all four stream blocks, while allowing either one pixel clock (for the single-stream controller) or two pixel clocks (for the remaining controllers). Update the Glymur MDSS schema example by adding the missing p2, p3, mst2link and mst3link register blocks. Without these, the bindings validation fails. Also replace the made-up register addresses with the actual addresses from the first controller to match the SoC devicetree description. Cc: stable@vger.kernel.org # v6.19 Fixes: 8f63bf908213 ("dt-bindings: display: msm: Document the Glymur DiplayPort controller") Fixes: 1aee577bbc60 ("dt-bindings: display: msm: Document the Glymur Mobile Display SubSystem") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/708518/ Link: https://lore.kernel.org/r/20260303-glymur-fix-dp-bindings-reg-clocks-v4-1-1ebd9c7c2cee@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-03-05Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR (net-7.0-rc3). No conflicts. Adjacent changes: net/netfilter/nft_set_rbtree.c fb7fb4016300 ("netfilter: nf_tables: clone set on flush only") 3aea466a4399 ("netfilter: nft_set_rbtree: don't disable bh when acquiring tree lock") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-03-05Merge tag 'net-7.0-rc3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net Pull networking fixes from Jakub Kicinski: "Including fixes from CAN, netfilter and wireless. Current release - new code bugs: - sched: cake: fixup cake_mq rate adjustment for diffserv config - wifi: fix missing ieee80211_eml_params member initialization Previous releases - regressions: - tcp: give up on stronger sk_rcvbuf checks (for now) Previous releases - always broken: - net: fix rcu_tasks stall in threaded busypoll - sched: - fq: clear q->band_pkt_count[] in fq_reset() - only allow act_ct to bind to clsact/ingress qdiscs and shared blocks - bridge: check relevant per-VLAN options in VLAN range grouping - xsk: fix fragment node deletion to prevent buffer leak Misc: - spring cleanup of inactive maintainers" * tag 'net-7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (138 commits) xdp: produce a warning when calculated tailroom is negative net: enetc: use truesize as XDP RxQ info frag_size libeth, idpf: use truesize as XDP RxQ info frag_size i40e: use xdp.frame_sz as XDP RxQ info frag_size i40e: fix registering XDP RxQ info ice: change XDP RxQ frag_size from DMA write length to xdp.frame_sz ice: fix rxq info registering in mbuf packets xsk: introduce helper to determine rxq->frag_size xdp: use modulo operation to calculate XDP frag tailroom selftests/tc-testing: Add tests exercising act_ife metalist replace behaviour net/sched: act_ife: Fix metalist update behavior selftests: net: add test for IPv4 route with loopback IPv6 nexthop net: ipv6: fix panic when IPv4 route references loopback IPv6 nexthop net: vxlan: fix nd_tbl NULL dereference when IPv6 is disabled net: bridge: fix nd_tbl NULL dereference when IPv6 is disabled MAINTAINERS: remove Thomas Falcon from IBM ibmvnic MAINTAINERS: remove Claudiu Manoil and Alexandre Belloni from Ocelot switch MAINTAINERS: replace Taras Chornyi with Elad Nachman for Marvell Prestera MAINTAINERS: remove Jonathan Lemon from OpenCompute PTP MAINTAINERS: replace Clark Wang with Frank Li for Freescale FEC ...
2026-03-05dt-bindings: remoteproc: qcom,sm8550-pas: Add Kaanapali CDSPJingyi Wang
Add remote processor PAS loader for Kaanapali CDSP processor, compatible with earlier SM8550 with minor difference: one more sixth "shutdown-ack" interrupt. It is not compatible with SM8650 because one memory region "global_sync_mem" is not managed by kernel on Kaanapali so it is removed in the remoteproc cdsp node. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260114-knp-remoteproc-v4-2-fcf0b04d01af@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-05dt-bindings: remoteproc: qcom,sm8550-pas: Add Kaanapali ADSPJingyi Wang
Document compatible for Qualcomm Kaanapali SoC ADSP PAS which looks fully compatible with SM8750, which can fallback to SM8550 except for one more interrupt ("shutdown-ack"). Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260114-knp-remoteproc-v4-1-fcf0b04d01af@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-05dt-bindings: arm: samsung: add compatible for samsung-j5y17lteKaustabh Chakraborty
Document board compatible for samsung-j5y17lte (exynos7870) Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://patch.msgid.link/20260304-exynos7870-j5y17lte-v1-1-eb25902c84c8@disroot.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-05dt-bindings: PCI: Add Andes QiLai PCIe supportRandolph Lin
Add the Andes QiLai PCIe node, which includes 3 Root Complexes. Only one example is required in the DTS bindings YAML file. Signed-off-by: Randolph Lin <randolph@andestech.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260225085504.3757601-2-randolph@andestech.com
2026-03-04dt-bindings: mux: Remove nodename pattern constraintsTommaso Merciai
The nodename pattern in created an unnecessary restriction that forced all mux nodes to be named with the 'mux-controller' prefix. This prevented valid use cases where mux functionality is part of other hardware blocks that should use more specific naming conventions. Remove the $nodename pattern constraints from both the 'select' keyword and the properties section of the mux-controller schema. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/dbe73c0777eca61cf14442f4082caae62b61805a.1769703480.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-03-04dt-bindings: net: dsa: maxlinear,mxl862xx: remove port labelDaniel Golle
The ports in the example device tree should not have a 'label' property. Labels for all user ports have been removed from an earlier submission, but this was overlooked in the case of the CPU port. Remove 'cpu' port label from the example. Suggested-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/61579de297eb636ec5f1e6c97d453e26abb0625d.1772507210.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-03-04dt-bindings: arm: qcom: Add ECS LIVA QC710Val Packett
Document the SC7180 (Snapdragon 7c) based ECS LIVA QC710 mini PC/devkit. Signed-off-by: Val Packett <val@packett.cool> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260120234029.419825-6-val@packett.cool Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-04dt-bindings: arm: qcom: Document PURWA-IOT-EVK boardYijie Yang
Document the device tree bindings for the PURWA-IOT-EVK board, which uses the Qualcomm X1P42100 SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260202073555.1345260-1-yijie.yang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-04dt-bindings: arm: qcom: Add Xiaomi Redmi Note 8TBarnabás Czémán
Document the Xiaomi Redmi Note 8 (willow). Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20260126-xiaomi-willow-v3-6-aad7b106c311@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-04dt-bindings: mmc: dwcmshc-sdhci: Fix resets array validationHuan He
The binding defines tuple-style reset-names items for some compatibles, which implicitly enforces a fixed array length via JSON Schema. Defining global maxItems for resets and reset-names causes these constraints to be intersected via allOf, resulting in an effective minItems equal to the global maxItems. This leads to dtbs_check failures reporting reset arrays as too short, even when the DTS provides the correct number of entries. Fixes: 30009a21f257 ("dt-bindings: mmc: sdhci-of-dwcmshc: Add Eswin EIC7700") Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com> Signed-off-by: Huan He <hehuan1@eswincomputing.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-04ASoC: dt-bindings: renesas,rz-ssi: Document RZ/G3L SoCBiju Das
Document RZ/G3L SSIF-2 bindings. The RZ/G3L SSIF-2 IP is identical to one found on the RZ/G2L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260304072000.6787-1-biju.das.jz@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-04dt-bindings: power: qcom,rpmpd: document the Eliza RPMh Power DomainsAbel Vesa
Document the RPMh Power Domains on the Eliza Platform. It is not compatible with any of the previous platforms, so dedicated compatible string is needed. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-04dt-bindings: gpio: mpfs-gpio: permit resetsConor Dooley
Both CoreGPIO and the hardened versions of it on mpfs and pic64gx have a reset pin. For the former, usually this is wired to a common fabric reset not managed by software and for the latter two the platform firmware takes them out of reset on first-party boards (or those using modified versions of the vendor firmware), but not all boards may take this approach. Permit providing a reset in devicetree for Linux, or other devicetree-consuming software, to use. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260303-irate-hungry-b54cda817e42@spud Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-03-03dt-bindings: net: qcom,ipa: Add sram property for describing IMEM sliceKonrad Dybcio
The IPA driver currently grabs a slice of IMEM through hardcoded addresses. Not only is that ugly and against the principles of DT, but it also creates a situation where two distinct platforms implementing the same version of IPA would need to be hardcoded together and matched at runtime. Instead, do the sane thing and accept a handle to said region directly. Don't make it required on purpose, as it's not there on ancient implementations (currently unsupported) and we're not yet done with filling the data across al DTs. Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260302-topic-ipa_imem-v6-2-c0ebbf3eae9f@oss.qualcomm.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-03-03dt-bindings: sram: qcom,imem: Allow modem-tables subnodeKonrad Dybcio
The IP Accelerator hardware/firmware owns a sizeable region within the IMEM, named 'modem-tables', containing various packet processing configuration data. It's not actually accessed by the OS, although we have to IOMMU-map it with the IPA device, so that presumably the firmware can act upon it. Allow it as a subnode of IMEM. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Alex Elder <elder@riscstar.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260302-topic-ipa_imem-v6-1-c0ebbf3eae9f@oss.qualcomm.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-03-03dt-bindings: power: supply: cpcap-battery: document monitored-battery propertySvyatoslav Ryhel
Document monitored-battery used to describe static battery cell properties. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260130134021.353688-2-clamor95@gmail.com Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2026-03-03dt-bindings: power: supply: max17042: drop formatting specifier |André Draszik
| denotes a literal (preformatted) block and is not necessary here. Drop them from this file. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20260302-max77759-fg-v3-3-3c5f01dbda23@linaro.org Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2026-03-03dt-bindings: power: supply: max17042: support shunt-resistor-micro-ohmsAndré Draszik
This binding supports the vendor-specific property maxim,rsns-microohm to describe the value of a shunt resistor required when measuring currents. shunt-resistor-micro-ohms is a standard property with the same meaning. Standard properties should be used instead of vendor- specific ones of similar intention when possible. Allow this standard property here, while also deprecating the existing vendor-specific property maxim,rsns-microohm. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20260302-max77759-fg-v3-2-3c5f01dbda23@linaro.org Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2026-03-03dt-bindings: power: supply: max17042: add support for max77759André Draszik
The Maxim MAX77759 is a companion PMIC intended for use in mobile phones and tablets. It is used on Google Pixel 6 and 6 Pro (oriole and raven). Amongst others, it contains a fuel gauge that is similar to the ones supported by this binding. The fuel gauge can measure battery charge and discharge current, battery voltage, battery temperature, and the Type C connector's temperature. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20260302-max77759-fg-v3-1-3c5f01dbda23@linaro.org Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2026-03-03dt-bindings: iio: adc: cpcap-adc: document Mot ADCSvyatoslav Ryhel
Add compatible for ADC used in Mot board. Separate compatible is required since ADC in the Mot board uses a unique set of configurations. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2026-03-03spi: dt-bindings: mpfs-spi: remove clock-namesConor Dooley
This binding documented clock-names, but never bothered to document what the name should be, rendering the property useless to software. It's not a required property, so it can just be removed without harming any software that conjured up it's own name for the clock, as they could not rely on it being there to begin with. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260303-spoils-snowbird-99f6e3a2dae3@spud Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-03spi: dt-bindings: mpfs-spi: permit resetsConor Dooley
CoreSPI, CoreQSPI and the hardened versions of them on mpfs and pic64gx have a reset pin. For the first two, usually this is wired to a common fabric reset not managed by software and for the latter two the platform firmware takes them out of reset on first-party boards (or those using modified versions of the vendor firmware), but not all boards may take this approach. Permit providing a reset in devicetree for Linux, or other devicetree-consuming software, to use. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260303-deceiver-rack-82f2b89eac40@spud Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-03dt-bindings: soc: microchip: mpfs-sys-controller: Add pic64gx compatibilityPierre-Henry Moussay
pic64gx is not compatible with mpfs because due to the lack of FPGA functionality some features are disabled. Notably, anything to do with FPGA fabric contents is not supported. Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-09 06:26:25 +0000