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2026-03-25ARM: dts: stm32: update i2c nodes interrupt/wakeup-source in stm32mp131Alain Volmat
Update all i2c nodes with the following properties: - replace interrupts with interrupts-extended and rely on exti - add the wakeup-source property Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Link: https://lore.kernel.org/r/20260224-stm32-i2c-dt-updates-v1-2-347cf6fca7d1@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-25ARM: dts: stm32: update i2c nodes interrupt/dma in stm32mp151Alain Volmat
Update all i2c nodes with the following properties: - replace interrupts with interrupts-extended and rely on exti - add dma properties Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Link: https://lore.kernel.org/r/20260224-stm32-i2c-dt-updates-v1-1-347cf6fca7d1@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-25ARM: dts: stm32: Add DT overlays for DH STM32MP13xx/STM32MP15xx DHSOMMarek Vasut
The following DTOs are supported on STM32MP15xx DHCOM PDK2: - DH 460-200 SRAM board in header X11 - DH 497-200 adapter card with EDT ETM0700G0EDH6 Parallel RGB panel - DH 505-200 adapter card with Chefree CH101OLHLWH-002 LVDS panel - DH 531-100 SPI/I2C board in header X21 - DH 531-200 SPI/I2C board in header X22 - DH 560-200 7" LCD board in header X12 - DH 638-100 mezzanine card with RPi 7" DSI panel attached on top - DH 672-100 expansion card, which contains CAN/FD transceiver and enables PDK2 to use one more CAN/FD interface The following DTOs are supported on STM32MP15xx DHCOM DRC02: - Enable configuration where the DHSOM inserted into the DRC02 has RSI 9116 WiFi populated on the SoM and where the microSD slot on the bottom of DRC02 must not be used. This permits a non-default configuration of the SoM and DRC02 board used for custom device setup with on-SoM WiFi. The following DTOs are supported on STM32MP15xx DHCOM PicoITX: - DH 548-200 adapter card with Multi-Inno MI0700D4T-6 7" DPI panel - DH 553-100 adapter card with Team Source Display TST043015CMHX 4.3" DPI panel - DH 626-100 adapter card with Chefree CH101OLHLWH-002 LVDS panel The following DTOs are supported on STM32MP15xx DHCOR Avenger96: - FDCAN1 on low-speed expansion X6 - FDCAN2 on low-speed expansion X6 - AT24C04 I2C EEPROM on low-speed expansion X6 I2C1 - AT24C04 I2C EEPROM on low-speed expansion X6 I2C2 - AT25AA010A SPI EEPROM on low-speed expansion X6 SPI2 - 96boards OV5640 mezzanine card with sensor connected to port J3. - DH 644-100 mezzanine card with Orisetech OTM8009A DSI panel - DH 644-100 mezzanine card with RPi 7" DSI panel The following DTOs are supported on STM32MP13xx DHCOR DHSBC: - joy-IT RB-TFT3.2-V2 240x320 SPI LCD and XPT2046 resistive touch controller Signed-off-by: Marek Vasut <marex@nabladev.com> Link: https://lore.kernel.org/r/20260121085347.10368-3-marex@nabladev.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-25arm: dts: stm32: enable CoreSight on the stm32mp135f-dk boardGatien Chevallier
Enable CoreSight peripherals on the stm32mp135f-dk board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20260226-debug_bus-v6-11-5d794697798d@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-25arm: dts: stm32: enable CoreSight on the stm32mp157c-ev1 boardGatien Chevallier
Enable CoreSight peripherals on the stm32mp157c-ev1 board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20260226-debug_bus-v6-10-5d794697798d@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-25arm: dts: stm32: enable CoreSight on stm32mp15xx-dkx boardsGatien Chevallier
Enable CoreSight peripherals on the stm32mp15xx-dkx boards. All boards including this file are embedding a dual core SoC so this change is applicable. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20260226-debug_bus-v6-9-5d794697798d@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-25arm: dts: stm32: enable the debug bus on stm32mp1x boardsGatien Chevallier
On stm32mp1x boards, enable the debug bus so we always try to probe the debug peripherals, if their status and the debug configuration allow it. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20260226-debug_bus-v6-8-5d794697798d@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-25arm: dts: stm32: introduce the debug bus for stm32mp1x platformsGatien Chevallier
Some peripherals cannot be probed if a debug configuration is not set in the BSEC. Introduce a debug bus that will check the debug subsystem accessibility before probing these peripheral drivers. Add Coresight peripheral nodes under this bus and add the appropriate access-controllers property to the HDP node. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20260226-debug_bus-v6-7-5d794697798d@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-03-25iio: accel: adxl380: fix typo in PART_ID register macroNikhil Gautam
Fix a typo in the ADXL380_PART_ID_REG macro name where it was incorrectly defined as ADLX380_PART_ID_REG. Also update its usage in adxl380_setup(). Signed-off-by: Nikhil Gautam <nikhilgtr@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2026-03-25riscv: dts: thead: beaglev-ahead: enable HDMI outputRobert Mazur
The BeagleV Ahead board includes a micro HDMI connector (Type-D) wired to the TH1520 SoC's HDMI transmitter. Enable the display pipeline by adding the HDMI connector node, connecting it to the HDMI controller, and activating the DPU and HDMI nodes. Signed-off-by: Robert Mazur <robert.mazur@imgtec.com> Signed-off-by: Drew Fustini <fustini@kernel.org>
2026-03-25Input: pegasus_notetaker - use HID definesOliver Neukum
The driver uses its own definitions for HID requests. This leads to duplication and obfuscation. Use HID's definitions. Signed-off-by: Oliver Neukum <oneukum@suse.com> Link: https://patch.msgid.link/20260325143256.371854-2-oneukum@suse.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: aiptek - use HID headersOliver Neukum
The driver uses its own definitions for HID requests. This leads to duplication and obfuscation. Use HID's definitions. Signed-off-by: Oliver Neukum <oneukum@suse.com> Link: https://patch.msgid.link/20260325143256.371854-1-oneukum@suse.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: goodix-berlin - report a resolution of 10 units/mmVal Packett
Without a reported resolution, userspace was assuming 1 unit/mm which is wildly wrong: a regular smartphone is clearly not 2.4 meters tall. Most applications do not care much for this kind of raw mm value, but Phosh's on-screen keyboard would accidentally trigger swipe-to-close gestures due to misinterpreting small movements as huge ones. Do what the older goodix.c driver does and set the resolution to 10 units/mm to make sure the numbers calculated by userspace are reasonable. Signed-off-by: Val Packett <val@packett.cool> Link: https://patch.msgid.link/20260321073242.556253-1-val@packett.cool Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25srcu: Use irq_work to start GP in tiny SRCUJoel Fernandes
Tiny SRCU's srcu_gp_start_if_needed() directly calls schedule_work(), which acquires the workqueue pool->lock. This causes a lockdep splat when call_srcu() is called with a scheduler lock held, due to: call_srcu() [holding pi_lock] srcu_gp_start_if_needed() schedule_work() -> pool->lock workqueue_init() / create_worker() [holding pool->lock] wake_up_process() -> try_to_wake_up() -> pi_lock Also add irq_work_sync() to cleanup_srcu_struct() to prevent a use-after-free if a queued irq_work fires after cleanup begins. Tested with rcutorture SRCU-T and no lockdep warnings. [ Thanks to Boqun for similar fix in patch "rcu: Use an intermediate irq_work to start process_srcu()" ] Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Paul E. McKenney <paulmck@kernel.org> Signed-off-by: Boqun Feng <boqun@kernel.org>
2026-03-25rcu: Use an intermediate irq_work to start process_srcu()Boqun Feng
Since commit c27cea4416a3 ("rcu: Re-implement RCU Tasks Trace in terms of SRCU-fast") we switched to SRCU in BPF. However as BPF instrument can happen basically everywhere (including where a scheduler lock is held), call_srcu() now needs to avoid acquiring scheduler lock because otherwise it could cause deadlock [1]. Fix this by following what the previous RCU Tasks Trace did: using an irq_work to delay the queuing of the work to start process_srcu(). [boqun: Apply Joel's feedback] [boqun: Apply Andrea's test feedback] Reported-by: Andrea Righi <arighi@nvidia.com> Closes: https://lore.kernel.org/all/abjzvz_tL_siV17s@gpd4/ Fixes: commit c27cea4416a3 ("rcu: Re-implement RCU Tasks Trace in terms of SRCU-fast") Link: https://lore.kernel.org/rcu/3c4c5a29-24ea-492d-aeee-e0d9605b4183@nvidia.com/ [1] Suggested-by: Zqiang <qiang.zhang@linux.dev> Tested-by: Andrea Righi <arighi@nvidia.com> Tested-by: Paul E. McKenney <paulmck@kernel.org> Tested-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Boqun Feng <boqun@kernel.org>
2026-03-25srcu: Push srcu_node allocation to GP when non-preemptiblePaul E. McKenney
When the srcutree.convert_to_big and srcutree.big_cpu_lim kernel boot parameters specify initialization-time allocation of the srcu_node tree for statically allocated srcu_struct structures (for example, in DEFINE_SRCU() at build time instead of init_srcu_struct() at runtime), init_srcu_struct_nodes() will attempt to dynamically allocate this tree at the first run-time update-side use of this srcu_struct structure, but while holding a raw spinlock. Because the memory allocator can acquire non-raw spinlocks, this can result in lockdep splats. This commit therefore uses the same SRCU_SIZE_ALLOC trick that is used when the first run-time update-side use of this srcu_struct structure happens before srcu_init() is called. The actual allocation then takes place from workqueue context at the ends of upcoming SRCU grace periods. [boqun: Adjust the sha1 of the Fixes tag] Fixes: 175b45ed343a ("srcu: Use raw spinlocks so call_srcu() can be used under preempt_disable()") Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Signed-off-by: Boqun Feng <boqun@kernel.org>
2026-03-25tools/sched_ext: Regenerate autogen enum headersCheng-Yang Chou
Regenerate enum_defs.autogen.h, enums.autogen.h and enums.autogen.bpf.h using the upstream scripts [1][2] to sync with recent kernel enum additions. [1] https://github.com/sched-ext/scx/blob/main/scripts/gen_enum_defs.py [2] https://github.com/sched-ext/scx/blob/main/scripts/gen_enums.py Signed-off-by: Cheng-Yang Chou <yphbchou0911@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2026-03-25srcu: Use raw spinlocks so call_srcu() can be used under preempt_disable()Paul E. McKenney
Tree SRCU has used non-raw spinlocks for many years, motivated by a desire to avoid unnecessary real-time latency and the absence of any reason to use raw spinlocks. However, the recent use of SRCU in tracing as the underlying implementation of RCU Tasks Trace means that call_srcu() is invoked from preemption-disabled regions of code, which in turn requires that any locks acquired by call_srcu() or its callees must be raw spinlocks. This commit therefore converts SRCU's spinlocks to raw spinlocks. [boqun: Add Fixes tag] Reported-by: Kumar Kartikeya Dwivedi <memxor@gmail.com> Fixes: c27cea4416a3 ("rcu: Re-implement RCU Tasks Trace in terms of SRCU-fast") Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Signed-off-by: Boqun Feng <boqun@kernel.org> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2026-03-25workqueue: unlink pwqs from wq->pwqs list in alloc_and_link_pwqs() error pathBreno Leitao
When alloc_and_link_pwqs() fails partway through the per-cpu allocation loop, some pool_workqueues may have already been linked into wq->pwqs via link_pwq(). The error path frees these pwqs with kmem_cache_free() but never removes them from the wq->pwqs list, leaving dangling pointers in the list. Currently this is not exploitable because the workqueue was never added to the global workqueues list and the caller frees the wq immediately after. However, this makes sure that alloc_and_link_pwqs() doesn't leave any half-baked structure, which may have side effects if not properly cleaned up. Fix this by unlinking each pwq from wq->pwqs before freeing it. No locking is needed as the workqueue has not been published yet, thus no concurrency is possible. Signed-off-by: Breno Leitao <leitao@debian.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2026-03-25workqueue: Better describe stall checkPetr Mladek
Try to be more explicit why the workqueue watchdog does not take pool->lock by default. Spin locks are full memory barriers which delay anything. Obviously, they would primary delay operations on the related worker pools. Explain why it is enough to prevent the false positive by re-checking the timestamp under the pool->lock. Finally, make it clear what would be the alternative solution in __queue_work() which is a hotter path. Signed-off-by: Petr Mladek <pmladek@suse.com> Acked-by: Song Liu <song@kernel.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2026-03-25selftests/bpf: Make reg_bounds test more robustAlexei Starovoitov
The verifier log output may contain multiple lines that start with 18: (bf) r0 = r6 teach reg_bounds to look for lines that have ';' in them, since reg_bounds test is looking for: 18: (bf) r0 = r6 ; R0=... R6=... Reviewed-by: Emil Tsalapatis <emil@etsalapatis.com> Link: https://lore.kernel.org/r/20260325012242.45606-1-alexei.starovoitov@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2026-03-25ASoC: SDCA: fix finding wrong entityShuming Fan
This patch fixes an issue like: where searching for the entity 'FU 11' could incorrectly match 'FU 113' first. The driver should first perform an exact match on the full string name. If no exact match is found, it can then fall back to a partial match. Fixes: 48fa77af2f4a ("ASoC: SDCA: Add terminal type into input/output widget name") Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Shuming Fan <shumingf@realtek.com> Link: https://patch.msgid.link/20260325110406.3232420-1-shumingf@realtek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-25Input: zinitix - use guard notation when acquiring mutexDmitry Torokhov
Guard notation simplifies code. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: wm97xx - use guard notation when acquiring mutexDmitry Torokhov
Guard notation simplifies code. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: wdt87xx_i2c - switch to using cleanup functionsDmitry Torokhov
Start using __free() and guard() primitives to simplify the code and error handling. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: tsc2007 - use guard notation when acquiring mutexesDmitry Torokhov
This makes the code more compact and error handling more robust. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: sx8654 - use IRQF_NOAUTOEN when requesting interruptDmitry Torokhov
Instead of requesting interrupt normally and immediately disabling it with call to disable_irq() use IRQF_NOAUTOEN to keep it disabled until it is needed. This avoids a tiny window when interrupt is enabled but not needed. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: sx8654 - use guard notation when acquiring spinlockDmitry Torokhov
Guard notation simplifies code. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: sur40 - use guard notation when acquiring spinlockDmitry Torokhov
Guard notation simplifies code. Also use list_first_entry() instead of list_entry() to emphasize intent. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: stmfts - use guard notation when acquiring mutexDmitry Torokhov
Guard notation simplifies code. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: raydium_i2c_ts - switch to using cleanup functionsDmitry Torokhov
Start using __free() and guard() primitives to simplify the code and error handling. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: pixcir_i2c_ts - use guard notation when acquiring mutexDmitry Torokhov
Guard notation simplifies code. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: novatek-nvt-ts - use guard notation when acquiring mutexDmitry Torokhov
Guard notation simplifies code. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25Input: mxs-lradc-ts - use guard notation when acquiring spinlockDmitry Torokhov
Guard notation simplifies code and shows critical section more clearly. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-03-25dt-bindings: mtd: mxc-nand: add missing compatible string and ref to ↵Frank Li
nand-controller-legacy.yaml Add compatible string fsl,imx51-nand, fsl,imx53-nand and fsl,imx35-nand. Add missinge properties dmas and dma-names. Change reg's maxItems to 2 because i.MX53 have addition NAND flash internal buffer space. Change ref to nand-controller-legacy.yaml allow legacy DT layout. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25dt-bindings: mtd: gpmi-nand: ref to nand-controller-legacy.yamlFrank Li
Ref to nand-controller-legacy.yaml instead nand-controller.yaml to allow legacy DT layout. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25dt-bindings: mtd: refactor NAND bindings and add nand-controller-legacy.yamlFrank Li
The modern NAND controller binding requires NAND chips to be described as child nodes of the controller, for example: nand-controller { ... nand@0 { /* raw NAND chip properties */ }; }; However, many existing device trees place NAND chip properties directly within the controller node because those controllers support only a single chip. This layout is still widely used by older platforms and by other DT consumers such as U-Boot. Migrating all existing users to the new layout will take time. Several kernel drivers, such as ams-delta.c, davinci_nand.c and fsmc_nand.c, still expect the legacy layout where raw NAND properties are defined in the controller node. To support both layouts during the transition: - Extract NAND chip-related properties into separate schemas (nand-property.yaml and raw-nand-property.yaml) from nand-chip.yaml and raw-nand-chip.yaml. - Introduce nand-controller-legacy.yaml to allow both the legacy and modern layouts. - Add a select condition in nand-controller.yaml to prevent node name pattern matching for fsl,* NAND controllers. Keep compatibility with existing device trees while allowing gradual migration to the modern binding structure. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: spinand: winbond: Clarify when to enable the HS bitMiquel Raynal
Above 104MHz when in fast dual or quad I/O reads, the delay between address and data cycles is too short. It is possible to reach higher frequencies, up to 166MHz, by adding a few more dummy cycles through the setting of the HS bit. Improve the condition for enabling this bit, and also make sure we set it at soon as we go over 104MHz. Fixes: f1a91175faaa ("mtd: spinand: winbond: Enable high-speed modes on w25n0xjw") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: rawnand: sunxi: introduce maximize variable user data lengthRichard Genoud
In Allwinner SoCs, user data can be added in OOB before each ECC data. For older SoCs like A10, the user data size was the size of a register (4 bytes) and was mandatory before each ECC step. So, the A10 OOB Layout is: [4Bytes USER_DATA_STEP0] [ECC_STEP0 bytes] [4bytes USER_DATA_STEP1] [ECC_STEP1 bytes] ... NB: the BBM is stored at the beginning of the USER_DATA_STEP0. Now, for H6/H616 NAND flash controller, this user data can have a different size for each step. So, we are maximizing the user data length to use as many OOB bytes as possible. Fixes: 88fd4e4deae8 ("mtd: rawnand: sunxi: Add support for H616 nand controller") Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: rawnand: sunxi: fix typos in commentsRichard Genoud
Fix lenghts -> lengths and chuncks -> chunks Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: rawnand: sunxi: change error prone variable nameRichard Genoud
In sunxi_nand_hw_ecc_ctrl_init(), i is used as a loop index variable and at the same time as the value used to set ECC mode in ECC control register. To prevent it from being re-used as a loop variable, let's change the naming to ecc_mode. No functional change. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: rawnand: sunxi: remove dead codeRichard Genoud
sunxi_nand_ooblayout_free() is only used in a code path where engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST So the other cases can be removed. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: rawnand: sunxi: make the code more self-explanatoryRichard Genoud
In sunxi_nfc_hw_ecc_{read,write}_chunk(), the ECC step was forced to 0, the reason is not trivial to get when reading the code. The explanation is that, from the NAND flash controller perspective, we are indeed at step 0 for user data length and ECC errors. Just add a const value with an explanation to clarify things. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: rawnand: sunxi: replace hard coded value by a define - take2Richard Genoud
The user data length (4) has been replaced almost all over the file, but 2 places were forgotten. The user data is placed before the ECC, for each step. So, in sunxi_nfc_hw_ecc_read_extra_oob(), the offset of the user data in OOB is indeed ((ecc->bytes + USER_DATA_SZ) * ecc->steps); And in sunxi_nand_ooblayout_ecc(), the offset of the ECC chunk in OOB is the same offset plus the current user data size: section * (ecc->bytes + USER_DATA_SZ) + USER_DATA_SZ; Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: rawnand: sunxi: do not count BBM bytes twiceRichard Genoud
BBM is already part of USER_DATA section, so we should not remove it twice This was working ok because we are on the safe size, advertising that there was 2 bytes less available than in reality. But we can't change old platforms, since it may lead to a different ECC strength, so, introduce a legacy flag for old platforms, and switch the new platforms to the correct count. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: rawnand: sunxi: fix sunxi_nfc_hw_ecc_read_extra_oobRichard Genoud
When dumping the OOB, the bytes at the end where actually copied from the beginning of the OOB instead of current_offset. That leads to something like: OOB: ff ff ff ff ff ff ff ff ea 19 00 3a 83 db aa 8d OOB: 99 09 c8 9a 90 36 35 7d aa 15 13 07 3d 97 b2 a4 OOB: a8 bb 19 b3 07 e9 f6 25 52 d7 1a 23 e2 7e 0a e4 OOB: 52 8a 09 d2 1a 86 3d cf b4 99 43 13 d3 90 33 0b OOB: ff ff ff ff ff ff ff ff ea 19 00 3a 83 db aa 8d OOB: 99 09 c8 9a 90 36 35 7d aa 15 13 07 3d 97 b2 a4 OOB: a8 bb 19 b3 07 e9 f6 25 52 d7 1a 23 e2 7e 0a e4 OOB: 52 8a 09 d2 1a 86 3d cf b4 99 43 13 d3 90 33 0b instead of: OOB: ff ff ff ff ff ff ff ff ea 19 00 3a 83 db aa 8d OOB: 99 09 c8 9a 90 36 35 7d aa 15 13 07 3d 97 b2 a4 OOB: a8 bb 19 b3 07 e9 f6 25 52 d7 1a 23 e2 7e 0a e4 OOB: 52 8a 09 d2 1a 86 3d cf b4 99 43 13 d3 90 33 0b OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff (example with BCH16, user data [8,0], no scrambling) *cur_off (offset from the beginning of the page) was compared to offset (offset from the beginning of the OOB), and then, the nand_change_read_column_op() sets the current position to the beginning of the OOB instead of OOB+offset Fixes: 15d6f118285f ("mtd: rawnand: sunxi: Stop supporting ECC_HW_SYNDROME mode") Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25mtd: rawnand: sunxi: sunxi_nand_ooblayout_free code clarificationRichard Genoud
The available length is really USER_DATA_LEN - 2 instead of just 2 (the user data length minus the BBM length) USER_DATA_LEN being 4, that doesn't change anything now, but if USER_DATA_LEN changes, it will. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-03-25drm: verisilicon: make vs_dc_platform_driver staticIcenowy Zheng
The platform_driver struct isn't export and is only used for module init/exit functions generated by module_platform_driver() macro. Make it static to prevent namespace pollution. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202603180616.TM6qYvIY-lkp@intel.com/ Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260324060806.2047121-1-zhengxingda@iscas.ac.cn
2026-03-25mfd: intel-lpss: Add Intel Nova Lake-H PCI IDsSaranya Gopal
Add Intel Nova Lake-H LPSS PCI IDs. Signed-off-by: Saranya Gopal <saranya.gopal@intel.com> Co-developed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260313100337.3471-1-ilpo.jarvinen@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2026-03-25MAINTAINERS: Update GPU driver maintainer informationJianmin Lv
I and Qianhai are GPU R&D engineers at Loongson, specializing in kernel driver development. We understand that the current Loongson GPU driver lacks dedicated maintenance resources because of some reasons. As Loongson GPU driver developers, we have both the capability and the responsibility to continuously maintain the Loongson GPU driver, ensuring minimal impact on its users. After internal discussions, our team has decided to recommend me and Qianhai to take over the maintenance responsibilities, and recommend Huacai, Mingcong and Ruoyao to help to review. And We'll continue to maintain it for current supported chips and drive future updates according to chip support plan. Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260320101012.22714-1-lvjianmin@loongson.cn
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-16 11:30:45 +0000