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2026-03-30dt-bindings: usb: richtek,rt1711h: Add Hynetek HUSB311Alexey Charkov
HUSB311 is a pin-compatible and register-compatible drop-in replacement for RT1711H, so add its compatible string to the existing binding. Link: https://www.hynetek.com/uploadfiles/site/219/news/0863c0c7-f535-4f09-bacd-0440d2c21088.pdf Link: https://dl.xkwy2018.com/downloads/RK3588S/03_Product%20Line%20Branch_Tablet/02_Key%20Device%20Specifications/HUSB311%20introduction%2020210526.pdf Link: https://www.richtek.com/assets/product_file/RT1711H/DS1711H-04.pdf Signed-off-by: Alexey Charkov <alchark@flipper.net> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260318-husb311-v4-3-69e029255430@flipper.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30dt-bindings: usb: richtek,rt1711h: Switch ETEK ET7304 to use a fallback ↵Alexey Charkov
compatible As stated in [1], ETEK ET7304 is identical to Richtek RT1715, except for the VID value in its registers, so reflect it in the bindings via a fallback compatible. As there are various TCPCI chips by different vendors reimplementing the registers and behavior of the RT1711H/RT1715, fallback compatibles will scale better. Link: https://lore.kernel.org/all/20260220-et7304-v3-2-ede2d9634957@gmail.com/ [1] Signed-off-by: Alexey Charkov <alchark@flipper.net> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260318-husb311-v4-2-69e029255430@flipper.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30dt-bindings: vendor-prefixes: Add Hynetek Semiconductor Co., Ltd.Alexey Charkov
Hynetek Semiconductor Co., Ltd. focuses on intelligent energy control technology, mainly for the intelligent fast charging and digital energy fields. Link: https://en.hynetek.com/ Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Alexey Charkov <alchark@flipper.net> Link: https://patch.msgid.link/20260318-husb311-v4-1-69e029255430@flipper.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30usb: dwc3: Add optional VBUS regulator support to SpacemiT K1Chukun Pan
Some SpacemiT K1 boards (like OrangePi R2S) provide USB VBUS through a controllable regulator. Add support for the optional vbus-supply property so the regulator can be properly managed in host mode instead of left always-on. Note that this doesn't apply to USB Hub downstream ports with different VBUS supplies. The enabled and disabled actions of the regulator are handled automatically by devm_regulator_get_enable_optional(). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Link: https://patch.msgid.link/20260326100010.3588454-2-amadeus@jmu.edu.cn Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30usb: dwc3: dwc3-generic-plat: spacemit: add support for K3 SoCYixun Lan
Add support for the DWC3 USB controller which found in SpacemiT K3 SoC. Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-2-308ea0e44038@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30dt-bindings: usb: dwc3: spacemit: add support for K3 SoCYixun Lan
Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC. The USB2.0 host controller in K3 SoC actually use DWC3 IP but only support USB2.0 functionality, thus in the hardware layer, it has only one USB2 PHY. While in K1 SoC, the USB controller has both USB2 and USB3 Combo PHY connected, but able to work in a reduced USB2.0 mode which requres only one USB2 PHY, leaves the USB3 Combo PHY to PCIe controller. So both K1 and K3 SoC are able to work in the USB2.0 mode which requires one PHY. Explicitly reduce number of phy property to minimal one. Signed-off-by: Yixun Lan <dlan@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-1-308ea0e44038@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30usb: gadget: udc: update outdated comment for renamed usb_gadget_udc_start()Kexin Sun
The function usb_gadget_udc_start() was renamed to usb_gadget_udc_start_locked() by commit 286d9975a838 ("usb: gadget: udc: core: Prevent soft_connect_store() race"). Update the comment in usb_gadget_udc_set_speed() accordingly. Assisted-by: unnamed:deepseek-v3.2 coccinelle Signed-off-by: Kexin Sun <kexinsun@smail.nju.edu.cn> Link: https://patch.msgid.link/20260321110006.8484-1-kexinsun@smail.nju.edu.cn Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30usb: typec: tcpci: support setting orientation via GPIOXu Yang
If the chip indicates its "Connection Orientation" standard output control in STANDARD_OUTPUT_CAPABILITIES register, it can do the thing by programming CONFIG_STANDARD_OUTPUT register. Due to the optional feature, the chip which not present this capability currently doesn't have a way to correctly set the data path. This add the support to set orientation via a simple GPIO. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Link: https://patch.msgid.link/20260319-support-setting-orientation-use-gpio-v4-2-ab6dfa8610c2@nxp.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30dt-bindings: usb: nxp,ptn5110: add optional orientation-gpios propertyXu Yang
The Type-C chip know the cable orientation and then normally will set the switch channel to correctly configure the data path. Some chips itself support to output the control signal by indicating the capability in bit[0] of STANDARD_OUTPUT_CAPABILITIES register and do it in CONFIG_STANDARD_OUTPUT register. For PTN5110 which doesn't present this capability currently there is no way to achieve the orientation setting. Add an optional "orientation-gpios" property to achieve the same purpose. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://patch.msgid.link/20260319-support-setting-orientation-use-gpio-v4-1-ab6dfa8610c2@nxp.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30dt-bindings: usb: document the Renesas UPD720201/UPD720202 USB 3.0 xHCI Host ↵Neil Armstrong
Controller Document the Renesas UPD720201/UPD720202 USB 3.0 xHCI Host Controller, which connects over PCIe and requires specific power supplies to start up. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260324-topic-sm8650-ayaneo-pocket-s2-upd-bindings-v2-1-b86a1543b76b@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30dt-bindings: usb: ti,usb8041: Support nested USB hubsAlexander Stein
Onboard USB hubs might be nested. Add the reference for the generic usb-hub.yaml binding and lift the restriction on peer-hub. A (downstream) hub might only be connected on USB High-Speed lines. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260313141220.1843488-1-alexander.stein@ew.tq-group.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30dt-bindings: usb: qcom,snps-dwc3: Document the Eliza compatibleAbel Vesa
Document the compatible for the Qualcomm Synopsys DWC3 glue controller found on Eliza SoC. It follows the same binding requirements as other recent Qualcomm SoCs, so add it to the existing schema conditionals covering the required properties. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260318-eliza-bindings-dwc3-v1-1-92bdf233cb87@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30usb: tegra: use MODULE_FIRMWARE if SOC is ENABLEDNicolas Chauvet
This allows to reduce the size of the initramfs by only selecting the related firmware when a given SOC is enabled. Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Link: https://patch.msgid.link/20260323140249.173603-1-kwizart@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30usb: gadget: bdc: validate status-report endpoint indicesPengpeng Hou
bdc_sr_xsf() decodes a 5-bit endpoint number from the hardware status report and uses it to index bdc->bdc_ep_array[] directly. The array is only allocated to bdc->num_eps for the current controller instance, so a status report can carry an endpoint number that still fits the 5-bit field but does not fit the runtime-sized endpoint table. Reject status reports whose endpoint number is outside bdc->num_eps before indexing the endpoint array. Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Justin Chen <justin.chen@broadcom.com> Link: https://patch.msgid.link/20260323121730.75245-1-pengpeng@iscas.ac.cn Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30usb: misc: iowarrior: use HID includesOliver Neukum
The driver uses its own definitions for HID requests. This leads to duplication and obfuscation. Use HID's definitions. Signed-off-by: Oliver Neukum <oneukum@suse.com> Link: https://patch.msgid.link/20260325171311.384010-2-oneukum@suse.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30usb: misc: appledisplay: use HID includesOliver Neukum
The driver uses its own definitions for HID requests. This leads to duplication and obfuscation. Use HID's definitions. Signed-off-by: Oliver Neukum <oneukum@suse.com> Link: https://patch.msgid.link/20260325171311.384010-1-oneukum@suse.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-03-30regulator: mt6315: add regulator suppliesMark Brown
Chen-Yu Tsai <wenst@chromium.org> says: This series is part of a broader collection of regulator related cleanups for MediaTek Chromebooks. This one covers the MT6315 PMIC. Patch 1 adds the names of the power supply inputs to the binding. Patch 2 adds the supply names from the DT binding change in patch 1 to the regulator descriptions in the driver. This patch has a checkpatch.pl warnings, but I wonder if it's because the context size for checking complex macros is not large enough. Device tree changes will be sent separately. The goal is to get the regulator tree as complete as possible. This includes adding supply names to other regulator DT bindings, and adding all the supply links to the existing DTs.
2026-03-30regulator: mt6315: Add regulator suppliesChen-Yu Tsai
The MT6315 family of PMICs has 4 buck regulators. Each regulator has a separate supply. Add these supplies to the driver. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://patch.msgid.link/20260326081050.1115201-3-wenst@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-30regulator: dt-bindings: mt6315: Add regulator suppliesChen-Yu Tsai
The MT6315 family of PMICs has 4 buck regulators. Each regulator has a separate supply. Add these supplies to the device tree binding. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://patch.msgid.link/20260326081050.1115201-2-wenst@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-30regulator: devres: Use enum regulator_get_type in internal functionsLuca Weiss
The enum regulator_get_type has been available since 2017, so use that enum instead of an "untyped" int in the three functions where "get_type" is used. No functional change intended. Suggested-by: Griffin Kroah-Hartman <griffin.kroah@fairphone.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://patch.msgid.link/20260330-regulator-devres-type-v1-1-d2c244576845@fairphone.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-30arm64: dts: qcom: sm8250: Add missing CPU7 3.09GHz OPPAlexander Koskovich
This resolves the following error seen on the ASUS ROG Phone 3: cpu cpu7: Voltage update failed freq=3091200 cpu cpu7: failed to update OPP for freq=3091200 Fixes: 8e0e8016cb79 ("arm64: dts: qcom: sm8250: Add CPU opp tables") Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260307-sm8250-cpu7-opp-v1-1-435f5f6628a1@pm.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30arm64: dts: qcom: sm8550-hdk: add support for the Display Card overlayVladimir Zapolskiy
The SM8550-HDK board may be connected to a Display Card external PCB, which is identical to the already supported SM8650-HDK Display Card, it provides a VTDR6130 display with Goodix Berlin Touch controller, see also commit bc90f56a1699 ("arm64: dts: sm8650-hdk: add support for the Display Card overlay") for additional details. Two overlays are added to support SM8550-HDK plus Display Card and SM8550-HDK plus Display Card plus Rear Camera Card setups. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260311001238.4191034-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30xfs: start gc on zonegc_low_space attribute updatesHans Holmberg
Start gc if the agressiveness of zone garbage collection is changed by the user (if the file system is not read only). Without this change, the new setting will not be taken into account until the gc thread is woken up by e.g. a write. Cc: stable@vger.kernel.org # v6.15 Fixes: 845abeb1f06a8a ("xfs: add tunable threshold parameter for triggering zone GC") Signed-off-by: Hans Holmberg <hans.holmberg@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Carlos Maiolino <cem@kernel.org>
2026-03-30xfs: don't decrement the buffer LRU count for in-use buffersChristoph Hellwig
XFS buffers are added to the LRU when they are unused, but are only removed from the LRU lazily when the LRU list scan finds a used buffer. So far this only happen when the LRU counter hits 0, which is suboptimal as buffers that were added to the LRU, but are in use again still consume LRU scanning resources and are aged while actually in use. Fix this by checking for in-use buffers and removing the from the LRU before decrementing the LRU counter. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Darrick J. Wong <djwong@kernel.org> Signed-off-by: Carlos Maiolino <cem@kernel.org>
2026-03-30xfs: switch (back) to a per-buftarg buffer hashChristoph Hellwig
The per-AG buffer hashes were added when all buffer lookups took a per-hash look. Since then we've made lookups entirely lockless and removed the need for a hash-wide lock for inserts and removals as well. With this there is no need to sharding the hash, so reduce the used resources by using a per-buftarg hash for all buftargs. Long after writing this initially, syzbot found a problem in the buffer cache teardown order, which this happens to fix as well by doing the entire buffer cache teardown in one places instead of splitting it between destroying the buftarg and the perag structures. Link: https://lore.kernel.org/linux-xfs/aLeUdemAZ5wmtZel@dread.disaster.area/ Reported-by: syzbot+0391d34e801643e2809b@syzkaller.appspotmail.com Reviewed-by: Darrick J. Wong <djwong@kernel.org> Tested-by: syzbot+0391d34e801643e2809b@syzkaller.appspotmail.com Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Brian Foster <bfoster@redhat.com> Signed-off-by: Carlos Maiolino <cem@kernel.org>
2026-03-30xfs: use a lockref for the buffer reference countChristoph Hellwig
The lockref structure allows incrementing/decrementing counters like an atomic_t for the fast path, while still allowing complex slow path operations as if the counter was protected by a lock. The only slow path operations that actually need to take the lock are the final put, LRU evictions and marking a buffer stale. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Brian Foster <bfoster@redhat.com> Reviewed-by: Darrick J. Wong <djwong@kernel.org> Signed-off-by: Carlos Maiolino <cem@kernel.org>
2026-03-30xfs: don't keep a reference for buffers on the LRUChristoph Hellwig
Currently the buffer cache adds a reference to b_hold for buffers that are on the LRU. This seems to go all the way back and allows releasing buffers from the LRU using xfs_buf_rele. But it makes xfs_buf_rele really complicated in differs from how other LRUs are implemented in Linux. Switch to not having a reference for buffers in the LRU, and use a separate negative hold value to mark buffers as dead. This simplifies xfs_buf_rele, which now just deal with the last "real" reference, and prepares for using the lockref primitive. This also removes the b_lock protection for removing buffers from the buffer hash. This is the desired outcome because the rhashtable is fully internally synchronized, and previously the lock was mostly held out of ordering constrains in xfs_buf_rele_cached. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Brian Foster <bfoster@redhat.com> Reviewed-by: Darrick J. Wong <djwong@kernel.org> Signed-off-by: Carlos Maiolino <cem@kernel.org>
2026-03-30mtd: spi-nor: sst: Fix write enable before AAI sequenceSanjaikumar V S
When writing to SST flash starting at an odd address, a single byte is first programmed using the byte program (BP) command. After this operation completes, the flash hardware automatically clears the Write Enable Latch (WEL) bit. If an AAI (Auto Address Increment) word program sequence follows, it requires WEL to be set. Without re-enabling writes, the AAI sequence fails. Add spi_nor_write_enable() after the odd-address byte program when more data needs to be written. Use a local boolean for clarity. Fixes: b199489d37b2 ("mtd: spi-nor: add the framework for SPI NOR") Cc: stable@vger.kernel.org Signed-off-by: Sanjaikumar V S <sanjaikumar.vs@dicortech.com> Tested-by: Hendrik Donner <hd@os-cillation.de> Reviewed-by: Hendrik Donner <hd@os-cillation.de> Signed-off-by: Pratyush Yadav (Google) <pratyush@kernel.org>
2026-03-30ASoC: amd: yc: Add DMI entry for HP Laptop 15-fc0xxxGilson Marquato Júnior
The HP Laptop 15-fc0xxx (subsystem ID 0x103c8dc9) has an internal DMIC connected to the AMD ACP6x audio coprocessor. Add a DMI quirk entry so the internal microphone is properly detected on this model. Tested on HP Laptop 15-fc0237ns with Fedora 43 (kernel 6.19.9). Signed-off-by: Gilson Marquato Júnior <gilsonmandalogo@hotmail.com> Link: https://patch.msgid.link/20260330-hp-15-fc0xxx-dmic-v2-v1-1-6dd6f53a1917@hotmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-30firmware: qcom: scm: Register gunyah watchdog deviceHrishabh Rajput
To restrict Gunyah watchdog initialization to Qualcomm platforms running under the Gunyah Hypervisor, register the watchdog device in the QCOM SCM driver. When Gunyah is not present or Gunyah emulates MMIO-based watchdog, we expect Qualcomm watchdog or ARM SBSA watchdog device to be present in the devicetree. First, we make sure we're running under the Gunyah Hypervisor. Then we move to check if any of the above mentioned watchdog device nodes are present, if not then we proceed to register the SMC-based Gunyah watchdog device. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Hrishabh Rajput <hrishabh.rajput@oss.qualcomm.com> Signed-off-by: Pavankumar Kondeti <pavan.kondeti@oss.qualcomm.com> Tested-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260311-gunyah_watchdog-v8-1-4c1c0689de22@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30clk: qcom: Add a driver for SM8750 GPU clocksKonrad Dybcio
Support the graphics clock controller for SM8750 for Graphics SW driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. Update the compatible for Graphics GX Clock Controller for SM8750 as the GX clock controller is a reuse of the Kaanapali driver. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-2-78292b40b053@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30dt-bindings: clock: qcom: Add SM8750 GPU clocksKonrad Dybcio
The SM8750 features a "traditional" GPU_CC block, much of which is controlled through the GMU microcontroller. GPU_CC block requires the MX and CX rail control and thus add the corresponding power-domains and require-opps. Additionally, there's an separate GX_CC block, where the GX GDSC is moved. Update the bindings to accommodate for SM8750 SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-1-78292b40b053@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30mtd: spi-nor: winbond: Fix locking support for w25q64jvmEliav Farber
The Winbond w25q64jvm supports block protection through the Status Register (SR) and provides a Top/Bottom (TB) protection bit. Enable SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB for this device to properly describe its locking capabilities. The device uses Status Register bit 5 as the TB bit and supports only three Block Protect (BP) bits. Therefore, do not set SPI_NOR_TB_SR_BIT6 or SPI_NOR_4BIT_BP. Reference: https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q64JV.1 Signed-off-by: Eliav Farber <farbere@amazon.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Pratyush Yadav (Google) <pratyush@kernel.org>
2026-03-30mtd: spi-nor: winbond: Fix locking support for w25q256jwmEliav Farber
The Winbond w25q256jwm device supports four Block Protect (BP) bits and uses Status Register bit 6 as the Top/Bottom (TB) protect bit. Update the flash parameters by enabling SPI_NOR_4BIT_BP and SPI_NOR_TB_SR_BIT6. Without these flags, the locking configuration is incorrect. Reference: https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q256JW.1 Signed-off-by: Eliav Farber <farbere@amazon.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Pratyush Yadav (Google) <pratyush@kernel.org>
2026-03-30ASoC: codecs: inline i2c_check_functionality checksThorsten Blum
Inline i2c_check_functionality() checks, since the function returns a boolean status rather than an error code. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://patch.msgid.link/20260329163152.366356-2-thorsten.blum@linux.dev Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-30arm64: dts: qcom: msm8916-samsung-coreprimeltevzw: add device treeMax McNamee
Samsung Galaxy Core Prime Verizon Wireless is a phone based on MSM8916. They are similar to the other Samsung devices based on MSM8916 with only a few minor differences. The device trees contain initial support with: - GPIO keys - Regulator haptic - SDHCI (internal and external storage) - USB Device Mode - UART (on USB connector via the SM5502 MUIC) - WCNSS (WiFi/BT) - Regulators - QDSP6 audio - Speaker/earpiece/headphones/microphones via digital/analog codec in MSM8916/PM8916 - WWAN Internet via BAM-DMUX - PMIC and charger - Touchscreen There are different variants of Core Prime, with some differences in NFC and MUIC. The common parts are shared in msm8916-samsung-fortuna-common.dtsi and msm8916-samsung-rossa-common.dtsi to reduce duplication. Signed-off-by: Max McNamee <maxmcnamee@proton.me> [Raymond: Refactor touchscreen and MUIC. Add commit messages.] Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260223220514.2556033-4-wonderfulshrinemaidenofparadise@postmarketos.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30dt-bindings: qcom: Document samsung,coreprimeltevzwRaymond Hackley
Document the new samsung,coreprimeltevzw device tree bindings used in msm8916-samsung-coreprimeltevzw. Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260223220514.2556033-3-wonderfulshrinemaidenofparadise@postmarketos.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30arm64: dts: qcom: msm8916-samsung-fortuna: Move SM5504 from rossa and ↵Raymond Hackley
refactor MUIC MUIC varies on fortuna/rossa devices, which could be either SM5502 or SM5504. Move SM5504 from msm8916-samsung-rossa-common to msm8916-samsung-fortuna-common and refactor MUIC. Disable MUIC by default in msm8916-samsung-fortuna-common, and explicitly specify them in each fortuna/rossa board. Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260223220514.2556033-2-wonderfulshrinemaidenofparadise@postmarketos.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30coresight: platform: check the availability of the endpoint before parseJie Gan
Check endpoint availability before parsing it. If parsing a connected endpoint fails, the probe is deferred until the endpoint becomes available, or eventually fails. In some legacy cases, a replicator has two output ports where one is disabled and the other is available. The replicator probe always fails because the disabled endpoint never becomes available for parsing. In addition, there is no need to defer probing a device that is connected to a disabled device, which improves probe performance. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Leo Yan <leo.yan@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20260320-add-availability-check-v1-1-b2e39cdeb6e0@oss.qualcomm.com
2026-03-30clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC supportJohn Crispin
The CMN PLL in IPQ8074 SoC supplies fixed clocks to the networking subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at 416.5 MHz. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20260311183942.10134-5-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074John Crispin
The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking subsystem. Add the related compatible for IPQ8074 to the ipq9574-cmn-pll generic schema. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260311183942.10134-4-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC supportJohn Crispin
The CMN PLL in IPQ6018 SoC supplies fixed clocks to the networking subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at 416.5 MHz. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20260311183942.10134-3-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018John Crispin
The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking subsystem. Add the related compatible for IPQ6018 to the ipq9574-cmn-pll generic schema. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260311183942.10134-2-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30arm64: dts: qcom: sdm670: add llccRichard Acayan
Add the Last Level Cache Controller (LLCC) for the SDM670. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260210021957.13357-4-mailingradian@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30arm64: dts: qcom: qcm6490-fairphone-fp5: Add front camera supportLuca Weiss
Add and configure the necessary nodes to enable the front camera (Samsung S5KJN1), connected to CSIPHY 3. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20260319-fp5-s5kjn1-v3-2-9cf4b8c09567@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30arm64: dts: qcom: qcm6490-fairphone-fp5: Sort pinctrl nodes by pinsLuca Weiss
As per DTS Coding Style, sort pinctrl subnodes by the "pins" property, in preparation to add more pinctrl states. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260319-fp5-s5kjn1-v3-1-9cf4b8c09567@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI bussesLuca Weiss
Enable the CCI I2C busses and add nodes for the EEPROMs found on the camera that are connected there. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20260320-milos-cci-v2-3-1947fc83f756@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30arm64: dts: qcom: milos: Add CCI bussesLuca Weiss
Add the nodes and the pinctrl for the CCI I2C busses on the Milos SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20260320-milos-cci-v2-2-1947fc83f756@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30soc: qcom: socinfo: Add SoC ID for SA8650PLei wang
Add SoC ID table entry for Qualcomm SA8650P. Signed-off-by: Lei wang <quic_leiwan@quicinc.com> Signed-off-by: Radu Rendec <rrendec@redhat.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260321152307.9131-3-rrendec@redhat.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30dt-bindings: arm: qcom,ids: Add SoC ID for SA8650PLei wang
Add unique ID for Qualcomm SA8650P SoC. Signed-off-by: Lei wang <quic_leiwan@quicinc.com> Signed-off-by: Radu Rendec <rrendec@redhat.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260321152307.9131-2-rrendec@redhat.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-16 01:19:36 +0000