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2026-05-13dt-bindings: display/msm: dp-controller: Allow DAI on SM8650 and othersKrzysztof Kozlowski
DisplayPort on Qualcomm SoCs like SM8650 and compatible SM8750 supports audio and there is already DTS having cells and sound-name-prefix. The "else:" clause for non-EDP and non-aux-bus cases already requires '#sound-dai-cells', so it should actually reference the dai-common.yaml for other properties, as pointed out by dtbs_check warnings like: sm8650-hdk-display-card-rear-camera-card.dtb: displayport-controller@af54000 (qcom,sm8650-dp): Unevaluated properties are not allowed ('sound-name-prefix' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/716452/ Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-2-34f4024c65dc@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-05-13dt-bindings: display/msm: dp-controller: Correct SM8650 IO rangeKrzysztof Kozlowski
DP on Qualcomm SM8650 come with nine address ranges, so describe the remaining ones as optional to keep ABI backwards compatible. Driver also does not need them to operate correctly. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/716450/ Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-1-34f4024c65dc@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-05-13drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpersJani Nikula
Add display specific helpers for getting the register offset, checking for equality and validity. Add them as static inlines for increased type safety. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/7fe12d4e5465778209ccf29359767a197b031dd9.1777972548.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13drm/i915/display: add struct intel_error_regs and use itJani Nikula
Add struct intel_error_regs, a display version of struct i915_error_regs, and use it. The goal is to reduce the dependency on i915 core types and headers. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/7f909c6b1f7ae623792b5abc3d31d4a682006e24.1777972548.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13drm/i915/display: add struct intel_irq_regs and use itJani Nikula
Add struct intel_irq_regs, a display version of struct i915_irq_regs, and use it. The goal is to reduce the dependency on i915 core types and headers. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/56118c2e40e171e898034a7bea6c8d14f515f5c1.1777972548.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13drm/i915/display: add typedef for intel_reg_t and use itJani Nikula
Add a typedef alias intel_reg_t for i915_reg_t, and use it exclusively in display code. The goal is to eventually define a distinct type for display, but for now just use an alias. In a handful of places include intel_display_reg_defs.h instead of i915_reg_defs.h to get the definition, and isolate the i915_reg_defs.h include there. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/f5bb0122143c39ce7f9ce8a1605a7637e569f7f8.1777972548.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13dt-bindings: interrupt-controller: Document PDC for Qualcomm Nord SoCShawn Guo
Document Power Domain Controller on Qualcomm Nord SoC. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260504080703.825328-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-05-13dt-bindings: arm: cpus: Add compatible qcom,oryon-1-5Shawn Guo
Qualcomm Oryon 1-5 is found on Nord SoC. Add compatible for it. $ cat /proc/cpuinfo ... CPU implementer : 0x51 CPU architecture: 8 CPU variant : 0x5 CPU part : 0x001 CPU revision : 4 Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260427004619.229843-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-05-13io_uring/rw: drop unused attr_type_mask from io_prep_rw_pi()Yang Xiuwei
io_prep_rw_pi() never used the attr_type_mask argument. Callers already validate sqe->attr_type_mask before invoking the helper (only IORING_RW_ATTR_FLAG_PI is supported today). Remove the dead parameter to avoid implying further interpretation happens here. Signed-off-by: Yang Xiuwei <yangxiuwei@kylinos.cn> Link: https://patch.msgid.link/20260513094303.866533-1-yangxiuwei@kylinos.cn Signed-off-by: Jens Axboe <axboe@kernel.dk>
2026-05-13evm: terminate and bound the evm_xattrs read bufferPengpeng Hou
evm_read_xattrs() allocates size + 1 bytes, fills them from the list of enabled xattrs, and then passes strlen(temp) to simple_read_from_buffer(). When no configured xattrs are enabled, the fill loop stores nothing and temp[0] remains uninitialized, so strlen() reads beyond initialized memory. Explicitly terminate the buffer after allocation, use snprintf() for each formatted line, and pass the accumulated length, without risk of truncation, to simple_read_from_buffer(). Fixes: fa516b66a1bf ("EVM: Allow runtime modification of the set of verified xattrs") Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn> Reviewed-by: Roberto Sassu <roberto.sassu@huawei.com> Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
2026-05-13integrity: Add support for sigv3 verification using ML-DSA keysStefan Berger
Add support for sigv3 signature verification using ML-DSA in pure mode. When a sigv3 signature is verified, first check whether the key to use for verification is an ML-DSA key and therefore uses a hashless signature verification scheme. The hashless signature verification method uses the ima_file_id structure directly for signature verification rather than its digest. Suggested-by: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Tested-by: Kamlesh Kumar <kam@juniper.net> Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
2026-05-13integrity: Refactor asymmetric_verify for reusabilityStefan Berger
Refactor asymmetric_verify for reusability. Have it call asymmetric_verify_common with the signature verification key and the public_key structure as parameters. sigv3 support for ML-DSA will need to check the public key type first to decide how to do the signature verification and therefore will have these parameters available for calling asymmetric_verify_common. Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Tested-by: Kamlesh Kumar <kam@juniper.net> Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
2026-05-13integrity: Check that algo parameter is within valid rangeStefan Berger
Check that the algo parameter passed to calc_file_id_hash is within valid range. Do this in asymmetric_verify_v3 since this value will also be passed to a hashless signature verification function from here. Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Tested-by: Kamlesh Kumar <kam@juniper.net> Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
2026-05-13integrity: Check for NULL returned by asymmetric_key_public_keyStefan Berger
Check for a NULL pointer returned by asymmetric_key_public_key and return -ENOKEY in this case. Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Tested-by: Kamlesh Kumar <kam@juniper.net> Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
2026-05-13drm/xe: Drop unused ggtt_balloon fieldMichal Wajdeczko
During recent GGTT refactoring we missed to drop now unused field from the xe_tile. Drop it now. Fixes: e904c56ba6e0 ("drm/xe: Rewrite GGTT VF initialization") Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/20260510205605.642-1-michal.wajdeczko@intel.com
2026-05-13platform/x86: int3472: Add more MSI AI evo laptopsAntti Laakso
The MSI prestige AI EVO 13 and 16 have the same camera configuration as model 14. Use the same platform data for all. Signed-off-by: Antti Laakso <antti.laakso@linux.intel.com> Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com> [Sakari Ailus: Use user-reported board name for model 16.] Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-05-13platform/x86: int3472: Match MSI laptop board nameAntti Laakso
Ensure MSI system is correct by checking board name too. Signed-off-by: Antti Laakso <antti.laakso@linux.intel.com> Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-05-13clk: rockchip: allow COMPILE_TEST buildsRosen Penev
COMMON_CLK_ROCKCHIP already gates the Rockchip clock objects inside the Rockchip clock Makefile. Allow selecting it for COMPILE_TEST and use it for the parent Makefile descent instead of ARCH_ROCKCHIP. The per-SoC Rockchip clock symbols already have COMPILE_TEST dependencies, so this exposes the existing build coverage to other architectures without selecting the Rockchip platform. Tested with: make LLVM=1 ARCH=loongarch drivers/clk/rockchip/ Assisted-by: Codex:GPT-5.5 Signed-off-by: Rosen Penev <rosenp@gmail.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20260509003602.956186-1-rosenp@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-05-13arm64: dts: amlogic: t7: Add PWM pinctrl nodesRonald Claveau
These pinctrl nodes are required by the PWM drivers to configure pin muxing at runtime. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr> Link: https://patch.msgid.link/20260326-add-emmc-t7-vim4-v5-4-d3f182b48e9d@aliel.fr Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-05-13Documentation/gpu/rfc: fix toctreeJani Nikula
Just one toctree is enough. The .rst suffixes are superfluous in the toctree. Fix indent. Add missing newline at the end of the file. Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Link: https://patch.msgid.link/c9678a78749a71cf86941f37116232dbc7c23b5f.1778238671.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13Documentation/gpu: add some tables of contents to large documentsJani Nikula
Some of the GPU documentation pages are quite long, with various levels of details. Add document internal tables of contents to the larger documents to make them easier to navigate. The index.rst in the sub-directories have toctrees, which provide similar overviews. Fix one missing newline at the end of drm-uapi.rst while at it, primarily because rst should have it, and secondarily because my editor rst mode refuses to save the file without it. Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Link: https://patch.msgid.link/e3f9357c0e8198cc48e69e2a3b8ca072c7ab92ca.1778238671.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13Documentation/gpu: limit main toctree depth to 2Jani Nikula
The main GPU documentation toctree has no limit to the toctree depth, which means the main GPU index page recursively includes all the headings in all of GPU documentation in the single table of contents. This makes getting any kind of overview of the documentation really difficult. Limit the main toctree depth to 2 i.e. show at most two levels of headings. Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://patch.msgid.link/cddd2d11c104132801510e3ab4e4b9ef3ea9cb6d.1778238671.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-13pinctrl-amd: enable IRQ for WACF2200 touchscreen on Lenovo Yoga 7 14AGP11Hardik Prakash
On Lenovo Yoga 7 14AGP11 (83TD), the WACF2200 touchscreen controller is wired via I2C2 (AMDI0010:02) with its interrupt on GPIO pin 157 (confirmed via ACPI _CRS GpioInt decode). After amd_gpio_irq_init() clears all GPIO interrupts at boot, pin 157 is never re-enabled, preventing the touchscreen from signalling the driver. Windows keeps GPIO 157 INTERRUPT_ENABLE (bit 11) and INTERRUPT_MASK (bit 12) set after initialisation. Add a DMI quirk to restore these bits after amd_gpio_irq_init() on this hardware. Assisted-by: Claude:claude-sonnet-4-6 Assisted-by: GPT-Codex:gpt-5.2-codex Signed-off-by: Hardik Prakash <hardikprakash.official@gmail.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-13gpio: zynq: Add eio gpio supportShubhrajyoti Datta
Add support for the EIO GPIO controller found on xa2ve3288 silicon. The EIO GPIO block provides access to multiplexed I/O pins exposed through the EIO interface. Only bank 0 and bank 1 are connected to external MIO pins, with 26 GPIOs per bank (52 GPIOs total). This change extends the Zynq GPIO driver to support the EIO GPIO variant. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://patch.msgid.link/20260512060917.2096456-4-shubhrajyoti.datta@amd.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-05-13dt-bindings: gpio: Add EIO GPIO compatible to gpio-zynqShubhrajyoti Datta
EIO (Extended IO) GPIO is a Xilinx IP block that exposes multiplexed I/O pins through an EIO interface. The EIO GPIO block has 2 banks with 26 GPIOs each (52 total). The GPIO width cannot be determined from the hardware registers, the driver relies on the compatible string to select the correct bank/pin configuration. A new compatible is therefore required. The block is currently present on xa2ve3288 silicon. The compatible string uses version 1.0 matching the IP core version. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://patch.msgid.link/20260512060917.2096456-3-shubhrajyoti.datta@amd.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-05-13dt-bindings: gpio: zynq: Sort compatible strings alphabeticallyShubhrajyoti Datta
Sort the compatible string alphabetically. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://patch.msgid.link/20260512060917.2096456-2-shubhrajyoti.datta@amd.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-05-13drm/hisilicon/hibmc: use clock to look up the PLL valueLin He
In the past, we use width and height to look up our PLL value. But actually the actual clock check is also necessnary. There are some resolutions that width and height same, but its clock different. Add the clock check when using pll_table to determine the PLL value. Fixes: da52605eea8f ("drm/hisilicon/hibmc: Add support for display engine") Signed-off-by: Lin He <helin52@huawei.com> Signed-off-by: Yongbang Shi <shiyongbang@huawei.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260509032302.2057227-5-shiyongbang@huawei.com
2026-05-13drm/hisilicon/hibmc: move display contrl config to hibmc_probe()Lin He
If there's no VGA output, this encoder modeset won't be called, which will cause displaying data from GPU being cut off. It's actually a common display config for DP and VGA, so move the vdac encoder modeset to driver load stage. Removed invalid bit configurations from `hibmc_display_ctrl` Fixes: 5294967f4ae4 ("drm/hisilicon/hibmc: Add support for VDAC") Signed-off-by: Lin He <helin52@huawei.com> Signed-off-by: Yongbang Shi <shiyongbang@huawei.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260509032302.2057227-4-shiyongbang@huawei.com
2026-05-13drm/hisilicon/hibmc: fix no showing when no connectors connectedLin He
Our chip support KVM over IP feature, so hibmc driver need to support displaying without any connectors plugged in. If no connectors are connected, the vdac connector status should be set to 'connected' to ensure proper KVM display functionality. Additionally, for previous-generation products that may lack hardware link support and thus cannot detect the monitor, the same approach should be applied to ensure VGA display functionality. * Add phys_state in the struct of dp and vdac to check physical outputs. * The 'epoch_counter' of the vdac connector is incremented when the physical status changes. For get_modes: using BMC modes for connector if no display is attached to phys VGA cable, otherwise use EDID modes by drm_connector_helper_get_modes, because KVM doesn't provide EDID reads. The polling mechanism for the KMS helper is enabled. Fixes: 4c962bc929f1 ("drm/hisilicon/hibmc: Add vga connector detect functions") Reported-by: Thomas Zimmermann <tzimmermann@suse.de> Closes: https://lore.kernel.org/all/0eb5c509-2724-4c57-87ad-74e4270d5a5a@suse.de/ Signed-off-by: Lin He <helin52@huawei.com> Signed-off-by: Yongbang Shi <shiyongbang@huawei.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Tested-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260509032302.2057227-3-shiyongbang@huawei.com
2026-05-13drm/hisilicon/hibmc: add updating link cap in DP detect()Lin He
In the past, the link cap is updated in link training at encoder enable stage, but the hibmc_dp_mode_valid() is called before it, which will use DP link's rate and lanes. So add the hibmc_dp_update_caps() in hibmc_dp_update_caps() to avoid some potential risks. Fixes: 607805abfb74 ("drm/hisilicon/hibmc: add dp mode valid check") Signed-off-by: Lin He <helin52@huawei.com> Signed-off-by: Yongbang Shi <shiyongbang@huawei.com> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260509032302.2057227-2-shiyongbang@huawei.com
2026-05-13drm/xe: Refactor emit_xy_fast_copy and emit_mem_copy functionsBalasubramani Vivekanandan
To perform copy, based on whether the platform supports service copy engines, either MEM_COPY or XY_FAST_COPY_BLT instruction is used. Length of both the instructions is same today and so they use a common define EMIT_COPY_DW. This is not true for the future platforms. Implement separate functions which return the length of the instruction to help in preparing for it. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260511123746.616662-8-balasubramani.vivekanandan@intel.com Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
2026-05-13drm/xe: Refactor emit_clear_link_copyBalasubramani Vivekanandan
Implement a function to return the length of the MEM_SET instruction. This is to prepare for future platforms where the length of MEM_SET instruction is expected to change. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260511123746.616662-7-balasubramani.vivekanandan@intel.com Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
2026-05-13drm/xe: Refactor emit_clear_main_copyBalasubramani Vivekanandan
Implement a function which returns the length of XY_FAST_COLOR_BLT instruction instead of hardcoding it inside the emit_clear_main_copy. In future platforms, the length of this instruction is expected to change and this patch helps in preparing for it. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260511123746.616662-6-balasubramani.vivekanandan@intel.com Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
2026-05-13drm/xe/devcoredump: Drop a FIXME in devcoredumpShekhar Chauhan
The FIXME says that xe_engine_snapshot_print.. is accessing persistent driver data, unlike what the FIXME says that it does. Drop the FIXME since the current code is not going to access the hardware while dumping. More details about this patch: https://patchwork.freedesktop.org/patch/703884/?series=161407&rev=1 The starting two feedbacks make sense and the original patch is wrong in adding those changes, but the last feedback is the one which highlights the point. Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260512055508.1380191-1-shekhar.chauhan@intel.com Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
2026-05-12stddef: Document designated initializer semantics for __TRAILING_OVERLAP()Gustavo A. R. Silva
Document the designated initializer behavior for overlapping storage between NAME and MEMBERS, and clarify the implications for static initialization to help avoid unintended overwrites. Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://patch.msgid.link/agD0R-kNbg9YMOCT@kspp Signed-off-by: Kees Cook <kees@kernel.org>
2026-05-13wifi: rtw88: remove rtw_txq_dequeueMartin Kaiser
Remove the rtw_txq_dequeue helper. It's a wrapper around ieee80211_tx_dequeue with just one caller. Call ieee80211_tx_dequeue directly in rtw_txq_push. There's no need to fetch txq for every frame, we can do this once outside of the rcu lock. Make the loop variable i unsigned long, it should have the same type as frames. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Acked-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260507082238.889656-1-martin@kaiser.cx
2026-05-13wifi: rtw89: check skb headroom before adding radiotapPing-Ke Shih
The radiotap headroom is allocated only if IEEE80211_CONF_MONITOR is set. However, it is potentially racing that SKB allocation without radiotap headroom but adding radiotap from matched PPDU status of another SKB. Add a check to avoid the case. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-15-pkshih@realtek.com
2026-05-13wifi: rtw89: phy: support PHY status IE-09 GEN2 for RTL8922DPing-Ke Shih
The format of PHY status IE-10 for RTL8922D is different from earlier chips. Fortunately only starting bit is different, but the layout is the same. Get the VHT/HE SIG-A value by corresponding mask accordingly. The IE-09 format of generation 0 and 1 are totally the same. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-14-pkshih@realtek.com
2026-05-13wifi: rtw89: phy: skip trailing 8-byte zeros of PHY status IE for RTL8922DPing-Ke Shih
Hardware reports a list of PHY status IE. In monitor mode, IE-09 of PHY status is enabled, and the report contains trailing 8-byte zeros, causing failed to parse and drop all IE information. The 8 zeros are recognize as IE type 0, but length of type 0 must be not 8 (reference to rtw89_phy_gen_def::physt_ie_len[0]). Check and skip them. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-13-pkshih@realtek.com
2026-05-13wifi: rtw89: phy: check length before parsing PHY status IEPing-Ke Shih
Hardware might report PHY status IE with unexpected length, and parser might access out of range. Check the length ahead. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-12-pkshih@realtek.com
2026-05-13wifi: rtw89: add debugfs entry of monitor mode options to capture HE-MU packetsPing-Ke Shih
To capture HE-MU packets, set BSS color and AID for specific connected station. The writing format: <bss color> <aid> For example, $ echo 0x4 0x16 > monitor_opts Read this entry to get current setting: bss_color=0x4 aid=0x16 By the way, add another sec2() function to create debugfs entries to prevent running smatch timeout. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-11-pkshih@realtek.com
2026-05-13wifi: rtw89: debug: make implementation of beacon_info entry in orderPing-Ke Shih
When adding more debugfs entries, the beacon_info entry becomes not in order. Move to correct location. Don't change logic at all. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-10-pkshih@realtek.com
2026-05-13wifi: rtw89: fill HE-SU/HE-TB/HE-MU/HE-EXT_SU radiotapPing-Ke Shih
Fill HE radiotap by PHY status IE-09/IE-10 which contains HE SIG-A/SIG-B respectively. The IE-10 may contain two content channels (if bandwidth is larger than 40MHz), and starting address of second content channel can be calculated by length of first content channel containing up to 15 user fields with 8-byte alignment. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-9-pkshih@realtek.com
2026-05-13wifi: rtw89: fill VHT radiotapPing-Ke Shih
Fill VHT radiotap by PHY status IE-09 which contains VHT SIG-A. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-8-pkshih@realtek.com
2026-05-13wifi: rtw89: move HE radiotap to an individual functionPing-Ke Shih
To implement more fields of HE radiotap, move the code to an individual function ahead. Not change logic at all. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-7-pkshih@realtek.com
2026-05-13wifi: rtw89: phy: enable IE-09/IE-10 PHY status report for monitor modePing-Ke Shih
The IE-09/IE-10 of PHY status contain SIG-A/SIG-B respectively, so enable them in monitor mode to have rich information. If the parser detects length invalid, ignore to reference IE-09/IE-10 to prevent accessing out of range. The RTL8922D is generation 2 of PHY status, which doesn't report SIG-B by IE-10, so not enable it. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-6-pkshih@realtek.com
2026-05-13wifi: rtw89: phy: define PHY status IE length for generationsPing-Ke Shih
Both RTL8922A and RTL8922D are WiFi 7 chips, but their IE length of PHY status are different. Define them accordingly. Generation 0: WiFi 6 chips Generation 1: WiFi 7 RTL8922A Generation 2: WiFi 7 RTL8922D Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-5-pkshih@realtek.com
2026-05-13wifi: rtw89: SNIFFER_MODE bit along IEEE80211_CONF_MONITORPing-Ke Shih
The SNIFFER_MODE bit can ignore filter rules, and receive packets to driver, so set the bit to accept all packets. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-4-pkshih@realtek.com
2026-05-13wifi: rtw89: add VHT beamformed to radiotapPing-Ke Shih
Set VHT beamformed bit by PHY status IE-01 report. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-3-pkshih@realtek.com
2026-05-13wifi: rtw89: add AMPDU to radiotapPing-Ke Shih
The RX desc can report current frame is in AMPDU, but no way point out if it is a last one in AMPDU. Update AMPDU reference only. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260506131000.1706298-2-pkshih@realtek.com
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-08 15:16:01 +0000