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2026-01-18irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BITHuacai Chen
irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently we pass acpi_pchpic->address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platforms. Also use readl() to read vec_count because readq() is only available on 64BIT platform. [ tglx: Make the cast explicit and use the casted address as argument for pch_pic_init() which takes a phys_addr_t as well. Fixup coding style. More sigh... ] Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260113085940.3344837-7-chenhuacai@loongson.cn
2026-01-18irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BITHuacai Chen
irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently the code passe acpi_pchmsi->msg_address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. [ tglx: Make the cast explicit and fixup coding style. ] Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260113085940.3344837-6-chenhuacai@loongson.cn
2026-01-18irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BITHuacai Chen
irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently the code passes acpi_htvec->address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platforms. [ tglx: Dereference _after_ the NULL pointer check, make the cast explicit and use the casted address as argument for htvec_init() which takes a phys_addr_t as well. Sigh... ] Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260113085940.3344837-5-chenhuacai@loongson.cn
2026-01-18irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BITHuacai Chen
iocsr_read64()/iocsr_write64() are only available on 64BIT LoongArch platform, so add and use a pair of helpers, i.e. read_isr()/write_isr() instead to make the driver work on both 32BIT and 64BIT platforms. This makes eoiintc_enable() a no-op for 32-bit as it is only required on 64-bit systems. [ tglx: Make the helpers inline and fixup the variable declaration order ] Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260113085940.3344837-4-chenhuacai@loongson.cn
2026-01-18irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BITHuacai Chen
irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently the code passes acpi_liointc->address to it. This can only work on 64BIT platforms because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. [ tglx: Make the cast explicit and use the casted address as argument for liointc_init() which takes a phys_addr_t as well. Sigh... ] Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260113085940.3344837-3-chenhuacai@loongson.cn
2026-01-18irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BITHuacai Chen
csr_read64() is only available on 64BIT LoongArch platform, so use the recently added adaptive csr_read() instead to make the driver work on both 32BIT and 64BIT platforms. This makes avecintc_enable() a no-op for 32-bit as it is only required on 64-bit systems. Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260113085940.3344837-2-chenhuacai@loongson.cn
2026-01-18Merge branch 'for-7.0/blk-pvec' into for-7.0/blockJens Axboe
* for-7.0/blk-pvec: types: move phys_vec definition to common header nvme-pci: Use size_t for length fields to handle larger sizes
2026-01-18iommu/amd: Fix error path in amd_iommu_probe_device()Vasant Hegde
Currently, the error path of amd_iommu_probe_device() unconditionally references dev_data, which may not be initialized if an early failure occurs (like iommu_init_device() fails). Move the out_err label to ensure the function exits immediately on failure without accessing potentially uninitialized dev_data. Fixes: 19e5cc156cb ("iommu/amd: Enable support for up to 2K interrupts per function") Cc: Rakuram Eswaran <rakuram.e96@gmail.com> Cc: Jörg Rödel <joro@8bytes.org> Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/202512191724.meqJENXe-lkp@intel.com/ Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18dt-bindings: watchdog: qcom-wdt: Document Glymur watchdogPankaj Patil
Add devicetree binding for watchdog present on Qualcomm's Glymur SoC Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18dt-bindings: watchdog: Convert mpc8xxx-wdt to YAMLJ. Neuschäfer
Convert mpc83xx-wdt.txt to YAML to enable automatic schema validation. Signed-off-by: J. Neuschäfer <j.ne@posteo.net> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18iommu/amd: Add support for nested domain attach/detachSuravee Suthikulpanit
Introduce set_dte_nested() to program guest translation settings in the host DTE when attaches the nested domain to a device. Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18iommu/amd: Refactor logic to program the host page table in DTESuravee Suthikulpanit
Introduce the amd_iommu_set_dte_v1() helper function to configure IOMMU host (v1) page table into DTE. This will be used later when attaching nested doamin. Also, remove obsolete warning when SNP is enabled and domain id is zero since this check is no longer applicable. Suggested-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18iommu/amd: Refactor persistent DTE bits programming into ↵Suravee Suthikulpanit
amd_iommu_make_clear_dte() To help avoid duplicate logic when programing DTE for nested translation. Note that this commit changes behavior of when the IOMMU driver is switching domain during attach and the blocking domain, where DTE bit fields for interrupt pass-through (i.e. Lint0, Lint1, NMI, INIT, ExtInt) and System management message could be affected. These DTE bits are specified in the IVRS table for specific devices, and should be persistent. Suggested-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18iommu/amd: Introduce gDomID-to-hDomID Mapping and handle parent domain ↵Suravee Suthikulpanit
invalidation Each nested domain is assigned guest domain ID (gDomID), which guest OS programs into guest Device Table Entry (gDTE). For each gDomID, the driver assigns a corresponding host domain ID (hDomID), which will be programmed into the host Device Table Entry (hDTE). The hDomID is allocated during amd_iommu_alloc_domain_nested(), and free during nested_domain_free(). The gDomID-to-hDomID mapping info (struct guest_domain_mapping_info) is stored in a per-viommu xarray (struct amd_iommu_viommu.gdomid_array), which is indexed by gDomID. Note also that parent domain can be shared among struct iommufd_viommu. Therefore, when hypervisor invalidates the nest parent domain, the AMD IOMMU command INVALIDATE_IOMMU_PAGES must be issued for each hDomID in the gdomid_array. This is handled by the iommu_flush_pages_v1_hdom_ids(), where it iterates through struct protection_domain.viommu_list. Suggested-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18iommu/amd: Add support for nested domain allocationSuravee Suthikulpanit
The nested domain is allocated with IOMMU_DOMAIN_NESTED type to store stage-1 translation (i.e. GVA->GPA). This includes the GCR3 root pointer table along with guest page tables. The struct iommu_hwpt_amd_guest contains this information, and is passed from user-space as a parameter of the struct iommu_ops.domain_alloc_nested(). Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18dt-bindings: watchdog: samsung-wdt: Split if:then: and constrain moreKrzysztof Kozlowski
Binding defined two if:then: blocks covering different conditions but not fully constraining the properties per each variant: 1. "if:" to require samsung,syscon-phandle, 2. "if:" with "else:" to narrow number of clocks and require or disallow samsung,cluster-index. This still did not cover following cases: 1. Disallow samsung,syscon-phandle when not applicable, 2. Narrow samsung,cluster-index to [0, 1], for SoCs with only two clusters. Solving this in current format would lead to spaghetti code, so re-write entire "if:then:" approach into mutually exclusive cases so each SoC appears only in one "if:" block. This allows to forbid samsung,syscon-phandle for S3C6410, and narrow samsung,cluster-index to [0, 1]. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18iommu/amd: Introduce struct amd_iommu_viommuSuravee Suthikulpanit
Which stores reference to nested parent domain assigned during the call to struct iommu_ops.viommu_init(). Information in the nest parent is needed when setting up the nested translation. Note that the viommu initialization will be introduced in subsequent commit. Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18dt-bindings: watchdog: samsung-wdt: Drop S3C2410Krzysztof Kozlowski
Samsung S3C2410 SoC was removed from Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of samsung,s3c2410-wdt compatible anymore and platform is so old, that there should be no out-of-tree users. If such existed, they would have enough of time to object dropping Samsung S3C2410 SoC removal from the kernel (which did not happen). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18iommu/amd: Add support for nest parent domain allocationSuravee Suthikulpanit
To support nested translation, the nest parent domain is allocated with IOMMU_HWPT_ALLOC_NEST_PARENT flag, and stores information of the v1 page table for stage 2 (i.e. GPA->SPA). Also, only support nest parent domain on AMD system, which can support the Guest CR3 Table (GCR3TRPMode) feature. This feature is required in order to program DTE[GCR3 Table Root Pointer] with the GPA. Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18iommu/amd: Always enable GCR3TRPMode when supported.Suravee Suthikulpanit
The GCR3TRPMode feature allows the DTE[GCR3TRP] field to be configured with GPA (instead of SPA). This simplifies the implementation, and is a pre-requisite for nested translation support. Therefore, always enable this feature if available. Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18iommufd: Introduce data struct for AMD nested domain allocationSuravee Suthikulpanit
Introduce IOMMU_HWPT_DATA_AMD_GUEST data type for IOMMU guest page table, which is used for stage-1 in nested translation. The data structure contains information necessary for setting up the AMD HW-vIOMMU support. Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18watchdog: s3c2410_wdt: Drop S3C2410 supportKrzysztof Kozlowski
Samsung S3C2410 SoC was removed from Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of samsung,s3c2410-wdt compatible and s3c2410-wdt platform device name, so drop both. This leaves the driver boundable only via compatibles, so drop any CONFIG_OF ifdefs. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18iommu/amd: Introduce helper function amd_iommu_update_dte()Suravee Suthikulpanit
Which includes DTE update, clone_aliases, DTE flush and completion-wait commands to avoid code duplication when reuse to setup DTE for nested translation. Also, make amd_iommu_update_dte() non-static to reuse in in a new nested.c file for nested translation. Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18dt-bindings: watchdog: samsung-wdt: Define cluster constraints top-levelKrzysztof Kozlowski
Properties should be always constrained in top-level part of the bindings, so move the samsung,cluster-index constrain from if: block. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18iommu/amd: Make amd_iommu_make_clear_dte() non-static inlineSuravee Suthikulpanit
This will be reused in a new nested.c file for nested translation. Also, remove unused function parameter ptr. Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18watchdog: rzv2h_wdt: Discard pm_runtime_put() return valueRafael J. Wysocki
Failing device probe due to pm_runtime_put() returning an error is not particularly useful. Returning an error code from pm_runtime_put() merely means that it has not queued up a work item to check whether or not the device can be suspended and there are many perfectly valid situations in which that can happen, like after writing "on" to the devices' runtime PM "control" attribute in sysfs for one example. It also happens when the kernel is configured with CONFIG_PM unset. Accordingly, update rzt2h_wdt_wdtdcr_init() to simply discard the return value of pm_runtime_put() and return success to the caller after invoking that function. This will facilitate a planned change of the pm_runtime_put() return type to void in the future. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18iommu/amd: Rename DEV_DOMID_MASK to DTE_DOMID_MASKSuravee Suthikulpanit
Also change the define to use GENMASK_ULL instead. There is no functional change. Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18watchdog: rz: Discard pm_runtime_put() return valuesRafael J. Wysocki
Failing a watchdog stop due to pm_runtime_put() returning a negative value is not particularly useful. Returning an error code from pm_runtime_put() merely means that it has not queued up a work item to check whether or not the device can be suspended and there are many perfectly valid situations in which that can happen, like after writing "on" to the devices' runtime PM "control" attribute in sysfs for one example. It also happens when the kernel is configured with CONFIG_PM unset. Accordingly, update rzg2l_wdt_stop() and rzv2h_wdt_stop() to simply discard the return value of pm_runtime_put(). This will facilitate a planned change of the pm_runtime_put() return type to void in the future. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18watchdog: Make API functions const correctKari Argillander
Many watchdog API functions do not modify the watchdog_device nor device. Mark their arguments as const to reflect this and improve const-correctness of the API. No functional change intended. Signed-off-by: Kari Argillander <kari.argillander@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18iommu/amd: Add support for hw_info for iommu capability querySuravee Suthikulpanit
AMD IOMMU Extended Feature (EFR) and Extended Feature 2 (EFR2) registers specify features supported by each IOMMU hardware instance. The IOMMU driver checks each feature-specific bits before enabling each feature at run time. For IOMMUFD, the hypervisor passes the raw value of amd_iommu_efr and amd_iommu_efr2 to VMM via iommufd IOMMU_DEVICE_GET_HW_INFO ioctl. Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2026-01-18irqchip/renesas-rzv2h: Prevent TINT spurious interrupt during resumeBiju Das
A glitch in the edge detection circuit can cause a spurious interrupt. The hardware manual recommends clearing the status flag after setting the ICU_TSSRk register as a countermeasure. Currently, a spurious interrupt is generated on the resume path of s2idle for the PMIC RTC TINT interrupt due to a glitch related to unnecessary enabling/disabling of the TINT enable bit. Fix this issue by not setting TSSR(TINT Source) and TITSR(TINT Detection Method Selection) registers if the values are the same as those set in these registers. Fixes: 0d7605e75ac2 ("irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260113125315.359967-2-biju.das.jz@bp.renesas.com
2026-01-18watchdog: imx7ulp_wdt: handle the nowayout optionOleksandr Suvorov
The module parameter `nowayout` indicates whether the watchdog should ever be allowed to stop, but the driver currently ignores this option. Pass the `nowayout` parameter to the watchdog core by setting the WDOG_NO_WAY_OUT flag accordingly. Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18watchdog: sbsa: Update the W_IIDR Implementer bit mask to 0xFFFNaina Mehta
The implementer mask defined in the driver [1] captures bits 0-10, whereas section C.4.2 of BSA specification [2] indicates that bits 0-11 of the W_IIDR register represent the implementer JEP106 code. Update the SBSA_GWDT_IMPL_MASK corresponding to bits 0-11, while at it update SBSA_GWDT_VERSION_MASK mask to use GENMASK. [1] #define SBSA_GWDT_IMPL_MASK 0x7FF [2] Implementer, bits [11:0] Contains the JEP106 code of the company that implemented the Generic Watchdog: Bits[11:8] The JEP106 continuation code of the implementer. Bit[7] Always 0 Bits [6:0] The JEP106 identity code of the implementer. Signed-off-by: Naina Mehta <naina.mehta@oss.qualcomm.com> Acked-by: Aaron Plattner <aplattner@nvidia.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18watchdog: Always return time left until watchdog times outGuenter Roeck
The watchdog core knows when the most recent keepalive was sent. It also knows the configured timeout. With that, it can always calculate and return the time left until a watchdog times out, even if its driver does not support it. Convert watchdog_get_timeleft() into a void function. It never returns an error after this patch is applied, so the error checks in the calling code are now pointless and can be removed. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Wim Van Sebroeck <wim@linux-watchdog.org> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18watchdog: iTCO: Drop vendor supportGuenter Roeck
iTCO vendor support was introduced in 2006 to support SuperMicro boards with Pentium 3 CPUs. It was extended in 2009 to support motherbords with broken BIOS (specifically Intel DG33TL). The code is long since obsolete, so let's drop support for it. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Wim Van Sebroeck <wim@linux-watchdog.org> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18compiler: Use __typeof_unqual__() for __unqual_scalar_typeof()Peter Zijlstra
The recent changes to get_unaligned() resulted in a new sparse warning: net/rds/ib_cm.c:96:35: sparse: sparse: incorrect type in argument 1 (different modifiers) @@ expected void * @@ got restricted __be64 const * @@ net/rds/ib_cm.c:96:35: sparse: expected void * net/rds/ib_cm.c:96:35: sparse: got restricted __be64 const * The updated get_unaligned_t() uses __unqual_scalar_typeof() to get an unqualified type. This works correctly for the compilers, but fails for sparse when the data type is __be64 (or any other __beNN variant). On sparse runs (C=[12]) __beNN types are annotated with __attribute__((bitwise)). That annotation allows sparse to detect incompatible operations on __beNN variables, but it also prevents sparse from evaluating the _Generic() in __unqual_scalar_typeof() and map __beNN to a unqualified scalar type, so it ends up with the default, i.e. the original qualified type of a 'const __beNN' pointer. That then ends up as the first pointer argument to builtin_memcpy(), which obviously causes the above sparse warnings. The sparse git tree supports typeof_unqual() now, which allows to use it instead of the _Generic() based __unqual_scalar_typeof(). With that sparse correctly evaluates the unqualified type and keeps the __beNN logic intact. The downside is that this requires a top of tree sparse build and an old sparse version will emit a metric ton of incomprehensible error messages before it dies with a segfault. Therefore implement a sanity check which validates that the checker is available and capable of handling typeof_unqual(). Emit a warning if not so the user can take informed action. [ tglx: Move the evaluation of USE_TYPEOF_UNQUAL to compiler_types.h so it is set before use and implement the sanity checker ] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Ian Rogers <irogers@google.com> Link: https://patch.msgid.link/87ecnp2zh3.ffs@tglx Closes: https://lore.kernel.org/oe-kbuild-all/202601150001.sKSN644a-lkp@intel.com/
2026-01-18ALSA: firewire: remove PCM buffer size constraint from isoc context headerTakashi Sakamoto
In the IEC 61883-1/6 packet streaming engine, the isochronous context header stores CIP headers. Previously, the header storage was limited to PAGE_SIZE, which constrained the maximum PCM buffer size. There is a function with configurable header size. Now the limitation is removed. Link: https://lore.kernel.org/r/20260117142823.440811-10-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2026-01-18firewire: core: add fw_iso_context_create() variant with header storage sizeTakashi Sakamoto
This commit adds a new variant of fw_iso_context_create() that allows specifying the size of the isochronous context header storage at allocation time. Link: https://lore.kernel.org/r/20260117142823.440811-9-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2026-01-18firewire: core: provide isoc header buffer size outside card driverTakashi Sakamoto
For single-channel isochronous contexts, the header storage size is hard-coded to PAGE_SIZE. which is inconvenient for protocol implementations requiring more space. This commit refactors the code to obtain the header storage size outside the 1394 OHCI driver. Link: https://lore.kernel.org/r/20260117142823.440811-8-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2026-01-18firewire: ohci: allocate isoc context header by kvmalloc()Takashi Sakamoto
Isochronous packet handling now runs in a workqueue context, where page faults is acceptable. This commit replaces __get_free_page() with kvmalloc() when allocating the isochronous context header buffer. Link: https://lore.kernel.org/r/20260117142823.440811-7-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2026-01-18firewire: core: add flags member for isochronous context structureTakashi Sakamoto
This is minor code refactoring to add a flag member to the isochronous context structure. At present, it is used only for the option to drop packets when the context header overflows. Link: https://lore.kernel.org/r/20260117142823.440811-6-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2026-01-18firewire: ohci: use cleanup helper for isoc context header allocationTakashi Sakamoto
Some cleanup helpers are useful in error path after memory allocation for header storage. Link: https://lore.kernel.org/r/20260117142823.440811-5-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2026-01-18firewire: ohci: code refactoring to use union for isoc multiple channel stateTakashi Sakamoto
In 1394 OHCI driver, some members of struct iso_context are only used for multi-channel isochronous contexts. This commit uses a union for these members to clearly separate multi-channel specific state. Link: https://lore.kernel.org/r/20260117142823.440811-4-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2026-01-18firewire: ohci: refactor isoc single-channel state using a unionTakashi Sakamoto
In 1394 OHCI driver, some members of struct iso_context are only used for single-channel isochronous contexts. This commit groups these members into a union. Link: https://lore.kernel.org/r/20260117142823.440811-3-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2026-01-18firewire: core: add function variants for isochronous context creationTakashi Sakamoto
The fw_iso_callback union was added by a commit ebe4560ed5c ("firewire: Remove function callback casts") to remove function pointer cast. That change affected the cdev layer of the core code, but it is more convenient for fw_iso_context_create() to accept the union directly. This commit renames and changes the existing function to take the union argument, and add static inline wrapper functions as variants. Link: https://lore.kernel.org/r/20260117142823.440811-2-o-takashi@sakamocchi.jp Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2026-01-18soc/tegra: pmc: Add PMC contextual functionsThierry Reding
Add implementations that take as argument a struct tegra_pmc * for most public APIs, as well as a function to obtain the PMC for any given device. This will allow transitioning away users from relying on a global variable storing the PMC context. Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-18soc/tegra: pmc: Do not rely on global variableThierry Reding
The reset action for changing the suspend mode back on failure can take a context-specific data argument that can be set to the PMC context in order to avoid relying on a global variable. Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-18soc/tegra: pmc: Use driver-private dataThierry Reding
Instead of relying on a global variable for the PMC context, use the driver-private data for sysfs attributes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-18soc/tegra: pmc: Use PMC context embedded in powergatesThierry Reding
The powergates exposed by the PMC have a pointer to the PMC context embedded. Use that embedded reference instead of relying on a global variable. For the core power domain a new structure needs to be introduced to wrap the generic PM domain and store the PMC context. Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-18soc/tegra: pmc: Pass PMC context as debugfs dataThierry Reding
Each debugfs file can have private data associated with it. Use this to pass the PMC context instead of relying on a global variable. Signed-off-by: Thierry Reding <treding@nvidia.com>