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2026-06-13octeontx2-af: npc: cn20k: add subbank search order controlRatheesh Kannoth
CN20K NPC MCAM is split into 32 subbanks that are searched in a predefined order during allocation. Lower-numbered subbanks have higher priority than higher-numbered ones. Add a runtime "srch_order" to control the order in which subbanks are searched during MCAM allocation. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Link: https://patch.msgid.link/20260609040453.711932-6-rkannoth@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13devlink: Implement devlink param multi attribute nested data valuesSaeed Mahameed
Devlink param value attribute is not defined since devlink is handling the value validating and parsing internally, this allows us to implement multi attribute values without breaking any policies. Devlink param multi-attribute values are considered to be dynamically sized arrays of u64 values, by introducing a new devlink param type DEVLINK_PARAM_TYPE_U64_ARRAY, driver and user space can set a variable count of u64 values into the DEVLINK_ATTR_PARAM_VALUE_DATA attribute. Implement get/set parsing and add to the internal value structure passed to drivers. This is useful for devices that need to configure a list of values for a specific configuration. example: $ devlink dev param show pci/... name multi-value-param name multi-value-param type driver-specific values: cmode permanent value: 0,1,2,3,4,5,6,7 $ devlink dev param set pci/... name multi-value-param \ value 4,5,6,7,0,1,2,3 cmode permanent Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Link: https://patch.msgid.link/20260609040453.711932-5-rkannoth@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13devlink: heap-allocate param fill buffers in devlink_nl_param_fillRatheesh Kannoth
devlink_nl_param_fill() kept two per-configuration-mode copies of union devlink_param_value plus a struct devlink_param_gset_ctx on the stack while building the Netlink reply. Allocate those with kcalloc() and kzalloc_obj() instead, and route failures through a single cleanup path so temporary buffers are always freed. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Link: https://patch.msgid.link/20260609040453.711932-4-rkannoth@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13octeontx2-af: npc: cn20k: debugfs enhancementsRatheesh Kannoth
Improve MCAM visibility and field debugging for CN20K NPC. - Extend "mcam_layout" to show enabled (+) or disabled state per entry so status can be verified without parsing the full "mcam_entry" dump. - Add "dstats" debugfs entry: for enabled MCAM indices, print hit deltas since the prior read by comparing hardware counters to a per-entry software baseline and advancing that baseline after each read (hardware counters are not cleared). - Add "mismatch" debugfs entry: lists MCAM entries that are enabled but not explicitly allocated, helping diagnose allocation/field issues. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Link: https://patch.msgid.link/20260609040453.711932-3-rkannoth@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13octeontx2-af: enforce single RVU AF probeRatheesh Kannoth
On Octeon series SoCs, the AF is an integrated device within the SoC, and hardware resources such as NPC, NIX and related blocks are global and coordinated by the AF driver. Physical and virtual functions request those resources via AF mailbox messages, so two AF driver instances cannot both own that global state; firmware exposes only one AF PCI function at boot and any further octeontx2-af PCI probe returns -EBUSY so software matches the single-AF model. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Link: https://patch.msgid.link/20260609040453.711932-2-rkannoth@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13Merge branch 'net-stmmac-fixes-for-maximum-tx-rx-queues-to-use-by-driver'Jakub Kicinski
Jakub Raczynski says: ==================== net/stmmac: Fixes for maximum TX/RX queues to use by driver When contributing other changes preparing functions for new XGMAC hardware https://lore.kernel.org/netdev/20260601162537.553512-1-j.raczynski@samsung.com/ there have been reports by Sashiko AI. All of issues are wrong DTS configuration, but kernel needs to handle it. ==================== Link: https://patch.msgid.link/20260611113358.3379518-1-j.raczynski@samsung.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13net/stmmac: Apply MTL_MAX queue limit if config missingJakub Raczynski
When "snps,rx-queues-to-use" or "tx-queues-to-use" config in DTS is provided current code will apply U8_MAX value for queues_to_use if there is input of higher value. But actual maximum number of supported queues is set via macro MTL_MAX_RX_QUEUES and MTL_MAX_TX_QUEUES, which currently have value of 8. This value of U8_MAX will be capped to value provided by core in DMA capabilities (dma_conf), but it does so only if core provides it. This is true for XGMAC (dwxgmac2) and some GMAC (dwmac4), but not for (dwmac1000). This capping is at later stage in stmmac_hw_init(), and during stmmac_mtl_setup() we might parse fields outside allocated memory if queues_to_use is over defines MTL_MAX_ values, for example following rx_queues_cfg is array of size of MTL_MAX_RX_QUEUES. Fix this by capping value to MTL_MAX during config parsing. Reported-by: Sashiko <sashiko-bot@kernel.org> Signed-off-by: Jakub Raczynski <j.raczynski@samsung.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://patch.msgid.link/20260611113358.3379518-3-j.raczynski@samsung.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13net/stmmac: Apply TBS config only to used queuesJakub Raczynski
While opening stmmac driver, there is enabling of TBS (Time-Based Scheduling) option in dma config. Currently this is executed for all possible TX queues via MTL_MAX_TX_QUEUES macro, but actual number of queues used might differ. While setting this is generally harmless, since memory for MTL_MAX_TX_QUEUES is allocated, it is incorrect, because it prepares config for unused queues. Change this to apply tbs config only to tx_queues_to_use. Co-developed-by: Chang-Sub Lee <cs0617.lee@samsung.com> Signed-off-by: Chang-Sub Lee <cs0617.lee@samsung.com> Signed-off-by: Jakub Raczynski <j.raczynski@samsung.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://patch.msgid.link/20260611113358.3379518-2-j.raczynski@samsung.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13net: airoha: Fix debugfs new-tuple display for IPv4 ROUTE entriesWayen.Yan
In airoha_ppe_debugfs_foe_show(), the second switch statement falls through from PPE_PKT_TYPE_IPV4_HNAPT/DSLITE to PPE_PKT_TYPE_IPV4_ROUTE, accessing hwe->ipv4.new_tuple for all three types. However, IPv4 ROUTE (3-tuple) entries do not contain a valid new_tuple — this field is only meaningful for NATted flows (HNAPT/DSLITE). For ROUTE entries, the memory at the new_tuple offset holds routing information, not NAT data, so displaying "new=" produces garbage output. Display new_tuple only for HNAPT and DSLITE, and let IPV4_ROUTE fall through to the default case. Fixes: 3fe15c640f38 ("net: airoha: Introduce PPE debugfs support") Link: https://lore.kernel.org/6a2b40ea.4dd82583.3a5c46.e5a2@mx.google.com Signed-off-by: Wayen.Yan <win847@gmail.com> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://patch.msgid.link/6a2be54b.ef98c1b2.3c3224.2ed8@mx.google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13net: airoha: Fix register index for Tx-fwd counter configurationWayen.Yan
In airoha_qdma_init_qos_stats(), the Tx-fwd counter configuration register uses the same index (i << 1) as the Tx-cpu counter, which overwrites the Tx-cpu configuration. The Tx-fwd counter value register correctly uses (i << 1) + 1, so the configuration register should use the same index. Fix the REG_CNTR_CFG index from (i << 1) to ((i << 1) + 1) so that the Tx-fwd counter is properly configured instead of clobbering the Tx-cpu counter config. Fixes: 20bf7d07c956 ("net: airoha: Add sched ETS offload support") Signed-off-by: Wayen.Yan <win847@gmail.com> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://patch.msgid.link/6a2b40e7.4dd82583.3a5c46.e566@mx.google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13tipc: restrict socket queue dumps in enqueue tracepointsLi Xiasong
tipc_sk_enqueue() runs with sk->sk_lock.slock held while the socket is owned by user context. The spinlock protects the backlog queue in this path, but it does not serialize against the socket owner consuming or purging sk_receive_queue. KASAN reported: CPU: 14 UID: 0 PID: 1050 Comm: tipc3 Not tainted 7.1.0-rc6+ #126 PREEMPT(lazy) Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.15.0-1 04/01/2014 Call Trace: <TASK> dump_stack_lvl+0x76/0xa0 lib/dump_stack.c:123 print_report+0xce/0x5b0 mm/kasan/report.c:482 kasan_report+0xc6/0x100 mm/kasan/report.c:597 __asan_report_load4_noabort+0x14/0x30 mm/kasan/report_generic.c:380 tipc_skb_dump+0x1327/0x16f0 net/tipc/trace.c:73 tipc_list_dump+0x208/0x2e0 net/tipc/trace.c:187 tipc_sk_dump+0xaf6/0xd60 net/tipc/socket.c:3996 trace_event_raw_event_tipc_sk_class+0x312/0x5a0 net/tipc/trace.h:188 tipc_sk_rcv+0xb1d/0x1d50 net/tipc/socket.c:2497 tipc_node_xmit+0x1c3/0x1440 net/tipc/node.c:1689 __tipc_sendmsg+0x97a/0x1440 net/tipc/socket.c:1512 tipc_sendmsg+0x52/0x80 net/tipc/socket.c:1400 sock_sendmsg+0x2f6/0x3e0 net/socket.c:825 splice_to_socket+0x7f9/0x1010 fs/splice.c:884 do_splice+0xe21/0x2330 fs/splice.c:936 __do_splice+0x153/0x260 fs/splice.c:1431 __x64_sys_splice+0x150/0x230 fs/splice.c:1616 x64_sys_call+0xeb5/0x2790 arch/x86/entry/syscall_64.c:41 do_syscall_64+0xf3/0x620 arch/x86/entry/syscall_64.c:63 entry_SYSCALL_64_after_hwframe+0x76/0x7e arch/x86/entry/entry_64.S:130 RIP: 0033:0x71624e8aafe2 Code: 08 0f 85 71 3a ff ff 49 89 fb 48 89 f0 48 89 d7 48 89 ce 4c 89 c2 4d 89 ca 4c 8b 44 24 08 4c 8b 4c 24 10 4c 89 5c 24 08 0f 05 <c3> 66 2e 0f 1f 84 00 00 00 00 00 66 2e 0f 1f 84 00 00 00 00 00 66 RSP: 002b:0000716157ffed68 EFLAGS: 00000246 ORIG_RAX: 0000000000000113 RAX: ffffffffffffffda RBX: 0000716157fff6c0 RCX: 000071624e8aafe2 RDX: 000000000000005f RSI: 0000000000000000 RDI: 0000000000000066 RBP: 0000716157ffed90 R08: 0000000000008000 R09: 0000000000000001 R10: 0000000000000000 R11: 0000000000000246 R12: ffffffffffffff00 R13: 0000000000000021 R14: 0000000000000000 R15: 00007fff89799c40 </TASK> The TIPC_DUMP_ALL tracepoints in tipc_sk_enqueue() also dump sk_receive_queue and can therefore dereference skbs that the socket owner has already dequeued or freed. Restrict these dumps to TIPC_DUMP_SK_BKLGQ, which matches the queue protected by the held spinlock. Keep the change limited to the enqueue path, where the unsafe queue dump is reachable while the socket is owned by user context. Fixes: 01e661ebfbad ("tipc: add trace_events for tipc socket") Cc: stable@vger.kernel.org Signed-off-by: Li Xiasong <lixiasong1@huawei.com> Reviewed-by: Tung Nguyen <tung.quang.nguyen@est.tech> Link: https://patch.msgid.link/20260611135647.3666727-1-lixiasong1@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13net: airoha: better handle MIBs for GDM ports with multiple devs attachedLorenzo Bianconi
In the context of a GDM port that can have multiple net_devices attached (GDM3 and GDM4), the HW counters (MIBs) are global for the GDM port. This cause duplicated stats reported to the kernel for the related net_device. The SoC supports a split MIB feature where each counter is tracked based on the relevant HW channel (NBQ) to account for this scenario and provide a way to select the related counter on accessing the MIB registers. Enable this feature for GDM3 and GDM4 and configure the relevant HW channel before updating the HW stats to report correct HW counter to the kernel for the related interface. Move the stats struct from port to dev since HW counter are now specific to the network device instead of the GDM port. Refactor airoha_update_hw_stats() to take airoha_eth and airoha_gdm_port parameters since the function operates on the entire port. Co-developed-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://patch.msgid.link/20260611-airoha-eth-multi-serdes-stats-v1-1-42442ae42064@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13octeontx2-af: fix NPC mailbox codes in mbox.hRatheesh Kannoth
Several NPC mailbox command IDs in the 0x601x range were assigned out of order. Renumber and reorder the M() definitions so each opcode matches the stable contract expected by userspace tools and applications. Fixes: 4e527f1e5c15 ("octeontx2-af: npc: cn20k: Add new mailboxes for CN20K silicon") Cc: Suman Ghosh <sumang@marvell.com> Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://patch.msgid.link/20260611083330.1652181-1-rkannoth@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13dt-bindings: net: dsa: Convert lan9303.txt to yaml formatFrank Li
Convert lan9303.txt to yaml format to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dtb: /soc/bus@50000000/i2c@53fec000/switch@a: failed to match any schema with compatible: ['smsc,lan9303-i2c'] Additional changes: - rename switch-phy to switch in example. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260610150533.515914-1-Frank.Li@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13ethernet: 3c509: Improve style of pnp_device_id array terminatorUwe Kleine-König (The Capable Hub)
To match how device-id array terminators look like for other device types drop `.id = ""` from it and let the compiler care for zeroing the entry. There are no changes in the compiled drivers, only the source looks nicer. Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/a0cd057e6a24b9d355b5e4bdfcdb812cdd1e4652.1781082923.git.u.kleine-koenig@baylibre.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13net: bcmgenet: Use weighted round-robin TX DMA arbitrationOvidiu Panait
Under heavy network traffic, we observed sporadic TX queue timeouts on the Raspberry Pi 4. The timeouts can be reproduced by stress testing the TX path with multiple concurrent iperf UDP streams: iperf3 -c <ip> -u -b0 -P16 -t60 NETDEV WATCHDOG: CPU: 0: transmit queue 0 timed out 2044 ms NETDEV WATCHDOG: CPU: 3: transmit queue 0 timed out 2004 ms Investigation showed that the timeouts are caused by the priority-based arbiter. Under heavy load the highest priority queue starves the lower priority ones, causing timeouts. The TX strict priority arbiter is not suitable for the default use case where all the traffic gets spread across all the TX queues. Therefore, to fix this, switch the TX DMA arbiter to Weighted Round-Robin, which services all queues, so they do not stall. The weights were chosen to follow the existing priority scheme: q0 gets the smallest weight, while q1-4 get the bulk of the TX bandwidth. Fixes: 1c1008c793fa ("net: bcmgenet: add main driver file") Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Link: https://patch.msgid.link/20260610085238.56300-1-ovidiu.panait.rb@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13selftests: net: add test for IPv4 devconf netlink notificationsFernando Fernandez Mancera
Introduce a new test, `ipv4_devconf_notify`, to verify that the kernel sends the appropriate netlink notifications when IPv4 devconf parameters are modified. The test depends on the newly introduced iproute2 command: `ip link set dev <ifname> inet` Signed-off-by: Fernando Fernandez Mancera <fmancera@suse.de> Link: https://patch.msgid.link/20260609204520.4670-3-fmancera@suse.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13ipv4: handle devconf post-set actions on netlink updatesFernando Fernandez Mancera
When IPv4 device configuration parameters are updated via netlink, the kernel currently only updates the value. This bypasses several post-modification actions that occur when these same parameters are updated via sysctl, such as flushing the routing cache or emitting RTM_NEWNETCONF notifications. This patch addresses the inconsistency by calling the devinet_conf_post_set() helper inside inet_set_link_af(). If a flush is required, we defer it until the netlink attribute parsing loop completes. This ensures consistent behavior and side-effects for devconf changes, regardless of whether they are initiated via sysctl or netlink. Reviewed-by: Nicolas Dichtel <nicolas.dichtel@6wind.com> Signed-off-by: Fernando Fernandez Mancera <fmancera@suse.de> Link: https://patch.msgid.link/20260609204520.4670-2-fmancera@suse.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13ipv4: centralize devconf sysctl handlingFernando Fernandez Mancera
The logic for handling IPv4 devconf sysctls is scattered. Notification and cache flushes are managed in devinet_conf_proc(), while a separate ipv4_doint_and_flush() function and DEVINET_SYSCTL_FLUSHING_ENTRY macro is used for properties that solely require a cache flush. This patch refactors the sysctl handling by introducing a centralized helper, devinet_conf_post_set(). This new function evaluates the changed attribute and handles all necessary operations like triggering netlink notifications. It returns a boolean indicating whether a routing cache flush is required. Note that the boolean is necessary as this function will be re-used for netlink IPv4 devconf handling where the cache flushing must wait until all the attributes have been processed. Finally, this is introducing a small change in behavior for IPV4_DEVCONF_ROUTE_LOCALNET. As commit d0daebc3d622 ("ipv4: Add interface option to enable routing of 127.0.0.0/8") intended, the cache flush should only be performed when ROUTE_LOCALNET changes from 1 to 0. Unfortunately, this was not true because while implementing it the DEVINET_SYSCTL_FLUSHING_ENTRY was used for the attribute, making the code related to it on devinet_conf_proc() dead. IPV4_DEVCONF_FORWARDING is still being handled separately as it requires more operations. Reviewed-by: Nicolas Dichtel <nicolas.dichtel@6wind.com> Signed-off-by: Fernando Fernandez Mancera <fmancera@suse.de> Link: https://patch.msgid.link/20260609204520.4670-1-fmancera@suse.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13samples/landlock: Add sandboxer UDP access controlMatthieu Buffet
Add environment variables to control associated access rights: - LL_UDP_BIND - LL_UDP_CONNECT_SEND Each one takes a list of ports separated by colons, like other list options. Signed-off-by: Matthieu Buffet <matthieu@buffet.re> Link: https://patch.msgid.link/20260611162107.49278-6-matthieu@buffet.re Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13selftests/landlock: Add tests for UDP sendMatthieu Buffet
Add tests specific to UDP sendmsg() in the protocol_* variants to ensure behaviour is consistent across AF_INET, AF_INET6 and AF_UNIX. Signed-off-by: Matthieu Buffet <matthieu@buffet.re> Link: https://patch.msgid.link/20260611162107.49278-5-matthieu@buffet.re [mic: Fix comment formatting, rebase] Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13selftests/landlock: Add tests for UDP bind/connectMatthieu Buffet
Make basic changes to the existing bind() and connect() test suite to cover UDP restriction. Signed-off-by: Matthieu Buffet <matthieu@buffet.re> Link: https://patch.msgid.link/20260611162107.49278-4-matthieu@buffet.re [mic: Update audit.connect_bound, fix comment formatting] Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13landlock: Add UDP send+connect access controlMatthieu Buffet
Add support for a second fine-grained UDP access right. LANDLOCK_ACCESS_NET_CONNECT_SEND_UDP controls the ability to set the remote port of a socket (via connect()) and to specify an explicit destination when sending a datagram, to override any remote peer set on a UDP socket (e.g. in sendto() or sendmsg()). It will be useful for applications that send datagrams, and for some servers too (those creating per-client sockets, which want to receive traffic only from a specific address). Similarly as for bind(), this access control is performed when configuring sockets, not in hot code paths. Add detection of when autobind is about to be required, and deny the operation if the process would not be allowed to call bind(0) explicitly. Autobind can only be performed in udp_lib_get_port() from code paths already controlled by LSM hooks: when connect()ing, sending a first datagram, and in some splice() EOF edge case which, afaiu, can only happen after a remote peer has been set. This invariant needs to be preserved to keep bind policies actually enforced. Signed-off-by: Matthieu Buffet <matthieu@buffet.re> Link: https://patch.msgid.link/20260611162107.49278-3-matthieu@buffet.re [mic: Add quick return for non-sandboxed tasks, fix sa_family dereferencing, fix comment formatting] Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13landlock: Add UDP bind() access controlMatthieu Buffet
Add support for a first fine-grained UDP access right. LANDLOCK_ACCESS_NET_BIND_UDP controls the ability to set the local port of a UDP socket (via bind()). It will be useful for servers (to start receiving datagrams), and for some clients that need to use a specific source port (e.g. mDNS requires to use port 5353) For obvious performance concerns, access control is only enforced when configuring sockets, not when using them for common send/recv operations. Bump ABI to allow userspace to detect and use this new right. Signed-off-by: Matthieu Buffet <matthieu@buffet.re> Link: https://patch.msgid.link/20260611162107.49278-2-matthieu@buffet.re [mic: Fix comment formatting] Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13landlock: Fix unmarked concurrent access to socket familyMatthieu Buffet
Socket family is read (twice) in a context where the socket is not locked, so another thread can setsockopt(IPV6_ADDRFORM) to write it concurrently. Add needed READ_ONCE() annotation. Use the proper macro to access __sk_common.skc_family like everywhere else. Fixes: fff69fb03dde ("landlock: Support network rules with TCP bind and connect") Signed-off-by: Matthieu Buffet <matthieu@buffet.re> Link: https://patch.msgid.link/20260609211511.85630-1-matthieu@buffet.re Link: https://patch.msgid.link/20260609211511.85630-2-matthieu@buffet.re [mic: Squash two patches, move variable to ease backport, fix comment formatting] Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13selftests/landlock: Explicitly disable audit in teardownsMaximilian Heyne
I'm seeing sporadic selftest failures, such as # RUN scoped_audit.connect_to_child ... # scoped_abstract_unix_test.c:314:connect_to_child:Expected 0 (0) == records.access (8) # connect_to_child: Test failed # FAIL scoped_audit.connect_to_child not ok 19 scoped_audit.connect_to_child This seems similar to what commit 3647a4977fb73d ("selftests/landlock: Drain stale audit records on init") tried to fix. However, the added drain loop is not effective. When setting the AUDIT_STATUS_PID, the kauditd_thread is woken up starting to send messages from the hold queue to the netlink. Depending on scheduling of this kthread not all messages might be send via the netlink in the 1 us interval. Therefore, instead of trying to drain the queue, let's just disable audit when running non-audit tests or more precisely disable it after audit-tests. This way we won't generate any new audit message that could interfere with the other tests. The comment saying that on process exit audit will be disabled is wrong. The closed file descriptor just causes an auditd_reset(), not a disablement. So future messages will be queued in the hold queue. Cc: stable@vger.kernel.org Fixes: 6a500b22971c ("selftests/landlock: Add tests for audit flags and domain IDs") Signed-off-by: Maximilian Heyne <mheyne@amazon.de> Link: https://patch.msgid.link/20260529-welsh-nagoya-b4d9ca60@mheyne-amazon [mic: Fix FD leak, update subject, call audit_cleanup() in audit_exec teardown] Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13selftests/landlock: Test SCOPE_SIGNAL on the SIGIO/fowner pgid pathBryam Vargas
Add regression tests for the LANDLOCK_SCOPE_SIGNAL handling of the asynchronous SIGIO delivery path (fcntl(F_SETOWN)) with a process-group owner. sigio_to_pgid_members covers the bypass: a sandboxed process at the head of its process group's PGID hlist (the default after fork()) arms F_SETOWN(-pgrp) + O_ASYNC and triggers the fan-out; the in-domain owner must be signaled (proving the trigger fired) while the non-sandboxed member of the group, outside the domain, must not. sigio_to_pgid_self covers the same-process guarantee: the owner is registered from a sandboxed non-leader thread, whose domain differs from the thread-group leader the kernel signals for a process-group owner. That leader belongs to the owner's own process and must still be signaled. Without the fix the first test sees the out-of-domain member signaled and the second sees the owner's own leader denied. Cc: stable@vger.kernel.org Signed-off-by: Bryam Vargas <hexlabsecurity@proton.me> Reviewed-by: Günther Noack <gnoack3000@gmail.com> Link: https://patch.msgid.link/43370e89f7a896a583bf33d1cd171d02630e61bf.1780614610.git.hexlabsecurity@proton.me [mic: Fix comment] Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13landlock: Fix LANDLOCK_SCOPE_SIGNAL bypass on the SIGIO pathBryam Vargas
LANDLOCK_SCOPE_SIGNAL must prevent a sandboxed process from signaling processes outside its Landlock domain. It can be bypassed through the asynchronous SIGIO delivery path. A sandboxed process that owns any file or socket can arm it with fcntl(fd, F_SETOWN, -pgid), fcntl(fd, F_SETSIG, SIGKILL) and O_ASYNC, so that an I/O event makes the kernel deliver the chosen signal to the whole process group. As the head of its process group's task list (the default position right after fork()) that group can also hold the non-sandboxed process that launched it, e.g. a supervisor or a security monitor. The sandbox can thus kill or signal the processes LANDLOCK_SCOPE_SIGNAL is meant to protect from it. The scope is enforced in hook_file_send_sigiotask() against the Landlock domain recorded at F_SETOWN time, not the live domain of the sender. control_current_fowner() decides whether to record that domain and skips recording it when the fowner target is in the caller's thread group, which is safe only for a single-task target (PIDTYPE_PID, PIDTYPE_TGID). For a process group (PIDTYPE_PGID) pid_task() returns only one member; recording is skipped whenever that member shares the caller's thread group, and hook_file_send_sigiotask() then lets the signal fan out to the whole group unchecked. Record the domain for every non single-process target so the scope is enforced against each group member at delivery time. That recording is necessary but not sufficient on its own: the kernel signals a process group through its members' thread-group leaders, and the leader of the registrant's own process can carry a different Landlock domain than the sibling thread that armed the owner. domain_is_scoped() would then deny that leader, even though commit 18eb75f3af40 ("landlock: Always allow signals between threads of the same process") requires same-process delivery to be allowed. hook_task_kill() avoids this by evaluating same_thread_group() live, per recipient; the SIGIO path instead delegates the whole decision to a single registration-time check, which a process-group fan-out cannot honor. So also record the registrant's thread group next to its domain and exempt it at delivery: hook_file_send_sigiotask() allows the signal whenever the recipient belongs to the registrant's own process, restoring the same-process guarantee while keeping out-of-domain group members blocked. The direct kill() path (hook_task_kill) already evaluates the live domain and is unaffected. Fixes: 18eb75f3af40 ("landlock: Always allow signals between threads of the same process") Cc: stable@vger.kernel.org Signed-off-by: Bryam Vargas <hexlabsecurity@proton.me> Reviewed-by: Günther Noack <gnoack3000@gmail.com> Link: https://patch.msgid.link/56bffc24f3d0d08b45a686a48e99766b0a0821fa.1780614610.git.hexlabsecurity@proton.me [mic: Check pid_type earlier and improve comment, fix commit message, fix comment formatting] Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13landlock: Demonstrate best-effort allowed_access filteringMickaël Salaün
Landlock provides best-effort sandboxing across ABI versions: applications request the rights they need, and on older kernels the unsupported rights are silently dropped from handled_access_* by the documented compatibility switch. The recommended pattern for landlock_add_rule(2) calls is to mirror this filtering at the rule level, which wasn't explicitly described in the exemple. Show the pattern explicitly in the filesystem and network rule examples by masking each rule's allowed_access against the ruleset's handled_access_* and adding the rule only when at least one bit remains set. This makes the recommended best-effort pattern self-documenting. Reviewed-by: Günther Noack <gnoack3000@gmail.com> Link: https://patch.msgid.link/20260513151856.148423-1-mic@digikod.net Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13landlock: Account all audit data allocations to user spaceMickaël Salaün
Mark the kzalloc_flex() of struct landlock_details with GFP_KERNEL_ACCOUNT so the allocation is charged to the calling task, like the other Landlock per-domain allocations which have used GFP_KERNEL_ACCOUNT forever. Every property of landlock_details is caller-attributable: allocated by landlock_restrict_self(2), owned by the caller's landlock_hierarchy, contents are the caller's pid, uid, comm, and exe_path, lifetime bounded by the caller's domain. While the caller may not know nor control the size of this allocation (i.e. exe_path), this data should still be accounted for it. The deciding factor is whether userspace can trigger the allocation, not whether the size of the data is known nor controlled by the caller. This aligns with the kmemcg accounting policy established by commit 5d097056c9a0 ("kmemcg: account certain kmem allocations to memcg"). No new failure modes: the hierarchy and ruleset are allocated before details and are already accounted, so landlock_restrict_self(2) already returns -ENOMEM under memcg pressure. This change widens that existing failure window slightly; it does not introduce a new error code. Cc: Günther Noack <gnoack@google.com> Cc: Paul Moore <paul@paul-moore.com> Cc: stable@vger.kernel.org Fixes: 1d636984e088 ("landlock: Add AUDIT_LANDLOCK_DOMAIN and log domain status") Link: https://patch.msgid.link/20260513180309.165840-1-mic@digikod.net Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13landlock: Set audit_net.sk for socket access checksMickaël Salaün
Set audit_net.sk in current_check_access_socket() to provide the socket object to audit_log_lsm_data(). This makes Landlock consistent with AppArmor, which always sets .sk for socket operations, and with SELinux's generic socket permission checks. The socket's local and foreign address information (laddr, lport, faddr, fport) is logged by the shared lsm_audit.c infrastructure when the socket has bound or connected state. Fields with zero values are suppressed by print_ipv4_addr()/print_ipv6_addr(), so the audit output is unchanged for the common case of bind denials on unbound sockets. For connect denials after a prior bind, the bound local address (laddr, lport) appears before the existing sockaddr fields (daddr, dest). No existing fields are removed or reordered, and the new field names (laddr, lport, faddr, fport) are standard audit fields already emitted by other LSMs through the same lsm_audit.c code path. Add a connect_tcp_bound audit test that binds to an allowed port and then connects to a denied one, verifying that the denial record reports laddr/lport from the bound socket in addition to the connect destination. Cc: Günther Noack <gnoack@google.com> Cc: Tingmao Wang <m@maowtm.org> Cc: stable@vger.kernel.org Fixes: 9f74411a40ce ("landlock: Log TCP bind and connect denials") Link: https://patch.msgid.link/20260612172757.1003481-1-mic@digikod.net Signed-off-by: Mickaël Salaün <mic@digikod.net>
2026-06-13Merge tag 'qcom-clk-for-7.2' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: - Add global, TCSR, and RPMh clock controllers for the Qualcomm Hawi mobile SoC - Add GX clock for Qualcomm Milos, and ensure that camera clock controller votes for interconnect bandwidth in order to ensure the TOP_GDSC can be turned on. - Add camera and video clock controllers for Qualcomm Hamoa and Purwa. Reduce the max_register of the display clock controller to avoid regmap attemting to dump protected registers. - Add global clock controller for the Qualcomm IPQ9650 SoC and add IPQ5332 support to the cmnpll driver. - Add missing USB2 PHY reset to the Qualcomm Nord NegCC. - Rework the Qualcomm PHY mux clock implementation as necessary for upcoming USB4 support. * tag 'qcom-clk-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (32 commits) clk: qcom: regmap-phy-mux: Rework the implementation clk: qcom: a53: Corrected frequency multiplier for 1152MHz clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC clk: qcom: gdsc: Support enabling interconnect path for power domain dt-bindings: clock: qcom,milos-camcc: Document interconnect path interconnect: Add devm_of_icc_get_by_index() as exported API for users clk: qcom: camcc-x1p42100: Add support for camera clock controller clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks clk: qcom: videocc-x1p42100: Add support for video clock controller dt-bindings: clock: qcom: Add X1P42100 camera clock controller dt-bindings: clock: qcom: Add X1P42100 video clock controller clk: qcom: nord: negcc: add support for the USB2 PHY reset dt-bindings: clock: qcom: add the definition for the USB2 PHY reset clk: qcom: clk-rpmh: Make all VRMs optional clk: qcom: Add support for global clock controller on Hawi clk: qcom: clk-alpha-pll: Add support for Taycan EHA_T PLL clk: qcom: Add Hawi TCSR clock controller driver clk: qcom: rpmh: Add support for Hawi RPMH clocks dt-bindings: clock: qcom: Add Hawi global clock controller dt-bindings: clock: qcom: Add Hawi TCSR clock controller ...
2026-06-13Merge tag 'clk-microchip-fixes-7.1' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clock fixes from Claudiu Beznea: - Fix the GMAC GCLK clock ID for the SAM9X7 SoC - Properly decrement the reference count of a struct device_node in pmc_register_ops() after it is no longer needed - Fix the MPFS peripheral driver registration failures by using the proper size and mapping for the output clocks array [sboyd@kernel.org: These all look non-critical so not taking for clk-fixes] * tag 'clk-microchip-fixes-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: keep securam node alive while mapping it clk: microchip: mpfs-ccc: fix peripheral driver registration failures after oob fix clk: at91: sam9x7: Fix gmac_gclk clock definition
2026-06-13Merge tag 'clk-microchip-7.2' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clk driver updates from Claudiu Beznea: - PIC32: Rename the clk-core.c Microchip clock driver to clk-pic32.c to better reflect its usage. - AT91: Remove peripheral clock ID 67 (GMAC TSU) for the SAM9X7 SoC, as it does not exist according to the documentation. - AT91: Rename the macb_clk peripheral clock to gmac_clk to match the documentation. - AT91: Add the I3C clock for the SAMA7D65 SoC. * tag 'clk-microchip-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: sama7d65: add peripheral clock for I3C clk: at91: sam9x7: Rename macb0_clk to gmac_clk clk: at91: sam9x7: Remove gmac peripheral clock with ID 67 clk: microchip: rename clk-core to clk-pic32
2026-06-13Merge tag 'spacemit-clk-for-7.2-1' of ssh://github.com/spacemit-com/linux ↵Stephen Boyd
into clk-spacemit Pull RISC-V SpacemiT clk driver updates from Yixun Lan: - Switch SpacemiT PCIe parent clock - Fix SpacemiT PCIe clock register offset - Add SpacemiT PCIe DBI clock * tag 'spacemit-clk-for-7.2-1' of ssh://github.com/spacemit-com/linux: clk: spacemit: k3: Add PCIe DBI clock dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs clk: spacemit: k3: Fix PCIe clock register offset clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
2026-06-13Merge tag 'v7.2-rockchip-clk1' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - Add gate-clocks for i2s outputs on Rockchip rk3588 - Allow compile-tests for the whole clock driver * tag 'v7.2-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: allow COMPILE_TEST builds clk: rockchip: rk3588: add GATE_GRF clocks for I2S MCLK output to IO soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset clk: rockchip: add helper to register auxiliary GRFs clk: rockchip: allow grf_type_sys lookup in aux_grf_table dt-bindings: clock: rockchip,rk3588-cru: add I2S MCLK output to IO clock IDs
2026-06-13Merge tag 'samsung-clk-7.2' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung Pull Samsung SoC clk driver updates from Krzysztof Kozlowski: - Exynos850: Mark APM (Active Power Management) I3C clocks as critical, because they are necessary for communication with firmware but we do not have any consumer of them so far. - Exynos990: Correct the parents of a few muxes and propagate rate requests up. * tag 'samsung-clk-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: exynos990: Fix PERIC0/1 USI clock types clk: samsung: exynos850: mark APM I3C clocks as critical
2026-06-13Merge tag 'ti-k3-sci-clk-for-v7.2' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into clk-ti Pull TI K3 SCI clock updates from Nishanth Menon: - Fix incorrect application of sizeof to a pointer type in TI sci-clk driver - Disable clock rate caching in the keystone clock driver to ensure accurate rate reporting * tag 'ti-k3-sci-clk-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: clk: keystone: sci-clk: fix application of sizeof to pointer clk: keystone: don't cache clock rate
2026-06-13Merge tag 'clk-canaan-7.2' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into clk-canaan Pull Canaan k230 clock support from Conor Dooley: - Driver and devicetree bindings for the Canaan k230 SoC clk controller Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'clk-canaan-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: clk: canaan: Add clock driver for Canaan K230 dt-bindings: clock: Add Canaan K230 clock controller
2026-06-13Merge tag 'renesas-clk-for-v7.2-tag2' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull more Renesas clk driver updates from Geert Uytterhoeven: - Add the Display Stream Compression (DSC) clock on Renesas R-Car V4H * tag 'renesas-clk-for-v7.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Drop unused pm_domain header file clk: renesas: r8a779g0: Add DSC clock clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro clk: renesas: rzg2l: Simplify SAM PLL configuration macro
2026-06-13Merge tag 'clk-meson-v7.2-1' of ssh://github.com/BayLibre/clk-meson into ↵Stephen Boyd
clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - Minor DT bindings fixes for the Amlogic T7 clock controllers * tag 'clk-meson-v7.2-1' of ssh://github.com/BayLibre/clk-meson: dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock dt-bindings: clock: amlogic: Fix redundant hyphen in "amlogic,t7-gp1--pll" string.
2026-06-13Merge tag 'socfpga_clk_update_for_v7.2' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into clk-socfpga Pull SoCFPGA clk driver update from Dinh Nguyen: - Implement the l3_main_free_clk on SoCFPGA agilex * tag 'socfpga_clk_update_for_v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: clk: socfpga: agilex: implement l3_main_free_clk
2026-06-13tcp: refine tcp_sequence() for the FIN exceptionEric Dumazet
Commit 0e24d17bd966 ("tcp: implement RFC 7323 window retraction receiver requirements") removed the special FIN case that was added in commit 1e3bb184e941 ("tcp: re-enable acceptance of FIN packets when RWIN is 0"). If a peer sends a segment containing data and a FIN flag before it learns about our window retraction and has a buggy TCP stack, it might place the FIN one byte beyond what it thinks is the right edge of the window (i.e., max_window_edge + 1). The data portion (end_seq - th->fin) will end exactly at max_window_edge. In this case, we will drop the packet if our receive queue is not empty, even though the data was sent within the window we previously allowed. Signed-off-by: Eric Dumazet <edumazet@google.com> Reviewed-by: Neal Cardwell <ncardwell@google.com> Reviewed-by: Kuniyuki Iwashima <kuniyu@google.com> Reviewed-by: Simon Baatz <gmbnomis@gmail.com> Link: https://patch.msgid.link/20260608151452.706822-1-edumazet@google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13Merge branch ↵Jakub Kicinski
'dpll-ice-add-generic-dpll-type-and-full-tx-reference-clock-control-for-e825' Grzegorz Nitka says: ==================== dpll/ice: Add generic DPLL type and full TX reference clock control for E825 NOTE: This series is intentionally submitted on net-next (not intel-wired-lan) as early feedback of DPLL subsystem changes is welcomed. In the past possible approaches were discussed in [1]. This series adds TX reference clock support for E825 devices and exposes TX clock selection and synchronization status via the Linux DPLL subsystem. Here is the high-level connection diagram for E825 device: +------------------------------------------------------------------+ | | | +-----------------------------+ | | | | | | | MAC | | | |+------------+-----+ | | | ||RX/1588 |PHC|tspll<----\ | | +---+----+ ||MUX +---+-^---| | | | | E | RX >---------------------> | >--\ | | | | T | | /----------------> | >-\| | | | | H |----+ | |+---------+----^---+ || | | | | 1 | TX <----|----------------+TX MUX < OCXO | || | | | | |PLL | | || |--------| || | | | +---+----+ | /----+ <-ext_ref<-||-|----|------ext_ref | E | RX >----/ | || |--------+ || | | | | T | | | || < SyncE | || | | | | H |----+ | |+-----------^------+ || | | | | 2 | TX <----------------/ | | /------||-/ | | | |PLL | +------------|-|------||------+ | +---+----+ /--/ | || | | . | RX >--- | | || | | . | | +----------|----|------||--+ | | . |----+ | +-^-+--^+ || | | | | TX <--- | |EEC|PPS| || | | | |PLL | | +-------+ || | | +---+----+ | | <-CLK0/| | | | E | RX >--- | | DPLL | | | | | T | | | | <-CLK1-/ | | | H |----+ | | | | | | X | TX <--- | | <---SMA---< | | |PLL | | | | | | +---+----+ | | <---GPS---< | | | | | | | | | | <---...---< | | | | | | | | | +-------+ | | | | External timing module | | | +--------------------------+ | +------------------------------------------------------------------+ E825 hardware contains a dedicated TX clock domain with per-port source selection behavior that is distinct from PPS handling and from board-level EEC distribution. TX reference clock selection is device-wide, shared across ports, and mediated by firmware as part of link bring-up. As a result, TX clock selection intent may differ from effective hardware configuration, and software must verify outcome after link-up. To support this, the series extends the DPLL core and the ice driver incrementally. The series also introduces DPLL_TYPE_GENERIC as a broad UAPI class for DPLL instances outside PPS/EEC categories. The intent is to keep type naming reusable and scalable across different ASIC topologies while preserving functional discoverability via driver/device context and pin topology. This follows netdev discussion guidance that UAPI type naming should avoid location-specific or vendor-specific taxonomy, because such labels do not scale across different ASIC designs. The function of a given DPLL instance is already discoverable from driver/device context and pin topology, and does not require an additional narrow type identifier in UAPI. At the same time, a separate DPLL object is still needed for E825 TX clock control/reporting semantics. Using DPLL_TYPE_GENERIC provides a reusable class for devices outside PPS/EEC without overfitting UAPI naming to one topology. The relevant discussion is in [2]. Series content - add a new generic DPLL type for devices outside PPS/EEC classes; - relax DPLL pin registration rules for firmware-described shared pins and extend pin notifications with a source identifier; - allow dynamic state control of SyncE reference pins where hardware supports it; - add CPI infrastructure for PHY-side TX clock control on E825C; - introduce a TX-clock DPLL device and TX reference clock pins (EXT_EREF0 and SYNCE) in the ice driver; - extend the Restart Auto-Negotiation command to carry a TX reference clock index; - implement hardware-backed TX reference clock switching, post-link verification, and TX synchronization reporting. TXCLK pins report TX reference topology only. Actual synchronization success is reported via DPLL lock status, updated after hardware verification: external TX references report LOCKED, while the internal ENET/TXCO source reports UNLOCKED. This provides reliable TX reference selection and observability on E825 devices using standard DPLL interfaces, without conflating user intent with effective hardware behavior. [1] https://lore.kernel.org/netdev/20250905160333.715c34ac@kernel.org/ [2] https://lore.kernel.org/netdev/20260402230626.3826719-1-grzegorz.nitka@intel.com/ ==================== Link: https://patch.msgid.link/20260607183045.1213735-1-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13ice: implement E825 TX ref clock control and TXC hardware sync statusGrzegorz Nitka
Build on the previously introduced TXC DPLL framework and implement full TX reference clock control and hardware-backed synchronization status reporting for E825 devices. E825 firmware may accept or override TX reference clock requests based on device-wide routing constraints and link conditions. Because the final selection becomes visible only after a link-up event, the driver splits the observation into two complementary signals: - TXCLK pin state reflects the requested TX reference clock (pf->ptp.port.tx_clk_req). After a link-up, the value is reconciled against the SERDES reference selector by ice_txclk_update_and_notify(); if firmware or auto-negotiation selected a different clock, tx_clk_req is overwritten so that pin state converges to the actual hardware selection. - TXC DPLL lock status reflects hardware synchronization: * LOCKED when an external TX reference is in use * UNLOCKED when falling back to ENET/TXCO, or when a requested external reference has not (yet) been accepted by hardware. Userspace observing only pin state therefore sees user intent, while lock status is the authoritative indicator of whether the requested clock is actually selected and synchronizing. This matches the DPLL subsystem model where pin state describes topology and device lock status describes signal quality. TX reference selection topology: - External references (SYNCE, EREF0) are represented as TXCLK pins - The internal ENET/TXCO clock has no pin representation; when selected, all TXCLK pins are reported DISCONNECTED With this change, TX reference clocks on E825 devices can be reliably selected, observed via standard DPLL interfaces, and monitored for effective synchronization through TXC DPLL lock status. Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Link: https://patch.msgid.link/20260607183045.1213735-14-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13ice: add Tx reference clock index handling to AN restart commandGrzegorz Nitka
Extend the Restart Auto-Negotiation (AN) AdminQ command with a new parameter allowing software to specify the Tx reference clock index to be used during link restart. This patch: - adds REFCLK field definitions to ice_aqc_restart_an - updates ice_aq_set_link_restart_an() to take a new refclk parameter and properly encode it into the command - keeps legacy behavior by passing REFCLK_NOCHANGE where appropriate This prepares the driver for configurations requiring dynamic selection of the Tx reference clock as part of the AN flow. Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Link: https://patch.msgid.link/20260607183045.1213735-13-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13ice: implement CPI support for E825CGrzegorz Nitka
Add full CPI (Converged PHY Interface) command handling required for E825C devices. The CPI interface allows the driver to interact with PHY-side control logic through the LM/PHY command registers, including enabling/disabling/selection of PHY reference clock. This patch introduces: - a new CPI subsystem (ice_cpi.c / ice_cpi.h) implementing the CPI request/acknowledge state machine, including REQ/ACK protocol, command execution, and response handling - helper functions for reading/writing PHY registers over Sideband Queue - CPI command execution API (ice_cpi_exec) and a helper for enabling or disabling Tx reference clocks (CPI 0xF1 opcode 'Config PHY clocking') - assurance of CPI transaction serialization into the CPI core. CPI REQ/ACK is a multi-step handshake and must be executed atomically per PHY. Centralize the lock in ice_cpi_exec() and use adapter-scoped per-PHY mutexes, which match the hardware sharing model across PFs. - addition of the non-posted write opcode (wr_np) to SBQ - Makefile integration to build CPI support together with the PTP stack This provides the infrastructure necessary to support PHY-side configuration flows on E825C and is required for advanced link control and Tx reference clock management. Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Link: https://patch.msgid.link/20260607183045.1213735-12-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13ice: introduce TXC DPLL device and TX ref clock pin framework for E825Grzegorz Nitka
E825 devices provide a dedicated TX clock (TXC) domain which may be driven by multiple reference clock sources, including external board references and port-derived SyncE. To support future TX clock control and observability through the Linux DPLL subsystem, introduce a separate TXC DPLL device (of DPLL_TYPE_GENERIC) and a framework for representing TX reference clock inputs. This change adds a new internal DPLL pin type (TXCLK) and registers TX reference clock pins for E825-based devices: - EXT_EREF0: a board-level external electrical reference - SYNCE: a port-derived SyncE reference described via firmware nodes The TXC DPLL device is created and managed alongside the existing PPS and EEC DPLL instances. TXCLK pins are registered directly or deferred via a notifier when backed by fwnode-described pins. A per-pin attribute encodes the TX reference source associated with each TXCLK pin. At this stage, TXCLK pin state callbacks and TXC DPLL lock status reporting are implemented as placeholders. Pin state getters always return DISCONNECTED, and the TXC DPLL is initialized in the UNLOCKED state. No hardware configuration or TX reference switching is performed yet. This patch establishes the structural groundwork required for hardware-backed TX reference selection, verification, and synchronization status reporting, which will be implemented in subsequent patches. Also signal dpll_init from the fwnode pin init error path so any notifier worker already blocked on it can drain, avoiding a flush_workqueue() deadlock during teardown. Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Link: https://patch.msgid.link/20260607183045.1213735-11-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13dpll: allow fwnode pins to attempt state change without capability bitGrzegorz Nitka
Pins registered with an fwnode may have .state_on_dpll_set implemented without advertising DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE upfront. Requiring the bit for fwnode pins ties firmware description to driver implementation details unnecessarily. Relax the capability check in dpll_pin_state_set() and dpll_pin_on_pin_state_set(): when a pin has an associated fwnode, bypass the capability gate and let the ops layer decide, returning -EOPNOTSUPP if .state_on_dpll_set is absent. Non-fwnode pins retain the original strict behavior. This is used later in the series by the SyncE_Ref output pin, which relies on the fwnode path for state control. Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Link: https://patch.msgid.link/20260607183045.1213735-10-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-06-13dpll: extend pin notifier with notification source IDGrzegorz Nitka
Extend the DPLL pin notification API to include a source identifier indicating where the notification originates. This allows notifier consumers to distinguish between notifications coming from an associated DPLL instance, a parent pin, or the pin itself. A new field, src_clock_id, is added to struct dpll_pin_notifier_info and is passed through all pin-related notification paths. Callers of dpll_pin_notify() are updated to provide a meaningful source identifier based on their context: - pin registration/unregistration uses the DPLL's clock_id, - pin-on-pin operations use the parent pin's clock_id, - pin changes use the pin's own clock_id. As introduced in the commit ("dpll: allow registering FW-identified pin with a different DPLL"), it is possible to share the same physical pin via firmware description (fwnode) with DPLL objects from different kernel modules. This means that a given pin can be registered multiple times. Driver such as ICE (E825 devices) rely on this mechanism when listening for the event where a shared-fwnode pin appears, while avoiding reacting to events triggered by their own registration logic. This change only extends the notification metadata and does not alter existing semantics for drivers that do not use the new field. Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Link: https://patch.msgid.link/20260607183045.1213735-9-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-08 20:03:09 +0000