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2026-01-22drm/msm/a8xx: Add UBWC v6 supportAkhil P Oommen
Adreno 840 GPU supports UBWC v6. Add support for this. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/700073/ Link: https://lore.kernel.org/r/20260121-kaana-gpu-support-v5-1-984848af12e4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-22drm/ci: ignore Gamma test failures on Qualcomm SC7180Dmitry Baryshkov
It seems, on SC7180 color conversion results are not included into the CRC calculation (unlike SM8350). The fails for SC7180 already lists CTM tests. Add gamma-related tests too. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Daniel Stone <daniels@collabora.com> Patchwork: https://patchwork.freedesktop.org/patch/699820/ Link: https://lore.kernel.org/r/20260121-dpu-sc7180-ignore-gamma-v1-1-84f2cc2beeb1@oss.qualcomm.com
2026-01-22drm/msm/dpu: Add DSPP GC driver to provide GAMMA_LUT DRM propertyFederico Amedeo Izzo
Add support for DSPP GC block in DPU driver for Qualcomm SoCs. Expose the GAMMA_LUT DRM property, which is needed to enable night light and basic screen color calibration. I used LineageOS downstream kernel as a reference and found the LUT format by trial-and-error on OnePlus 6. Tested on oneplus-enchilada (sdm845-mainline 6.16-dev) and xiaomi-tissot (msm8953-mainline 6.12/main). Tested-by: David Heidelberg <david@ixit.cz> # Pixel 3 (next-20251018) Tested-by: Guido Günther <agx@sigxcpu.org> # on sdm845-shift-axolotl Signed-off-by: Federico Amedeo Izzo <federico@izzo.pro> Tested-by: Steev Klimaszewski <threeway@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/682102/ Link: https://lore.kernel.org/r/20251019-dpu-add-dspp-gc-driver-v3-1-840491934e56@izzo.pro Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-01-21Input: appletouch - fix potential race between resume and openDmitry Torokhov
Take the input device's mutex in atp_resume() and atp_recover() to make sure they are not racing with open and close methods, and use input_device_enabled() helper to see if communication with the device needs to be restarted after resume. Link: https://patch.msgid.link/uuwucixxc2ckd6ul6yv5mdvkc3twytg4tg5a5vhfqg6m2qcodc@klaco6axglbm Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21crypto: Add ML-DSA crypto_sig supportDavid Howells
Add verify-only public key crypto support for ML-DSA so that the X.509/PKCS#7 signature verification code, as used by module signing, amongst other things, can make use of it through the common crypto_sig API. Signed-off-by: David Howells <dhowells@redhat.com> Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org> cc: Eric Biggers <ebiggers@kernel.org> cc: Lukas Wunner <lukas@wunner.de> cc: Ignat Korchagin <ignat@cloudflare.com> cc: Stephan Mueller <smueller@chronox.de> cc: Herbert Xu <herbert@gondor.apana.org.au> cc: keyrings@vger.kernel.org cc: linux-crypto@vger.kernel.org
2026-01-21HID: i2c-hid: Add FocalTech FT8112Daniel Peng
Information for touchscreen model HKO/RB116AS01-2 as below: - HID :FTSC1000 - slave address:0X38 - Interface:HID over I2C - Touch control lC:FT8112 - I2C ID: PNP0C50 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Acked-by: Jiri Kosina <jkosina@suse.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://patch.msgid.link/20251117094041.300083-2-Daniel_Peng@pegatron.corp-partner.google.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21dt-bindings: input: i2c-hid: Introduce FocalTech FT8112Daniel Peng
Create new binding file for the FocalTech FT8112 due to new touchscreen chip. Confirm its compatible, reg for the device via vendor, and set the interrupt and reset gpio to map for Skywalker platform. FocalTech FT8112 also uses vcc33/vccio power supply. Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251117094041.300083-1-Daniel_Peng@pegatron.corp-partner.google.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21ARM: dts: qcom: switch to RPMPD_* indicesDmitry Baryshkov
Use generic RPMPD_* defines for power domain instead of using platform-specific defines. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251211-rework-rpmhpd-rpmpd-v2-2-a5ec4028129f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-21drm/nouveau/disp: Set drm_mode_config_funcs.atomic_(check|commit)Lyude Paul
Apparently we never actually filled these in, despite the fact that we do in fact technically support atomic modesetting. Since not having these filled in causes us to potentially forget to disable fbdev and friends during suspend/resume, let's fix it. Signed-off-by: Lyude Paul <lyude@redhat.com> Cc: stable@vger.kernel.org Reviewed-by: Dave Airlie <airlied@redhat.com> Link: https://patch.msgid.link/20260121191320.210342-1-lyude@redhat.com
2026-01-21drm/nouveau: implement missing DCB connector types; gracefully handle ↵Alex Ramírez
unknown connectors * Implement missing DCB connectors in uconn.c previously defined in conn.h. * Replace kernel WARN_ON macro with printk message to more gracefully signify an unknown connector was encountered. With this patch, unknown connectors are explicitly marked with value 0 (DCB_CONNECTOR_VGA) to match the tested current behavior. Although 0xff (DCB_CONNECTOR_NONE) may be more suitable, I don't want to introduce a breaking change. Fixes: 8b7d92cad953 ("drm/nouveau/kms/nv50-: create connectors based on nvkm info") Link: https://download.nvidia.com/open-gpu-doc/DCB/1/DCB-4.0-Specification.html#_connector_table_entry Signed-off-by: Alex Ramírez <lxrmrz732@rocketmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> [Lyude: Remove unneeded parenthesis around nvkm_warn()] Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251213005327.9495-3-lxrmrz732@gmail.com
2026-01-21drm/nouveau: add missing DCB connector typesAlex Ramírez
* Add missing DCB connectors in conn.h as per the NVIDIA DCB specification. A lot of connector logic was rewritten for Linux v6.5; some display connector types went unaccounted-for which caused kernel warnings on devices with the now-unsupported DCB connectors. This patch adds all of the DCB connectors as defined by NVIDIA to the dcb_connector_type enum to bring back support for these connectors to the new logic. Fixes: 8b7d92cad953 ("drm/nouveau/kms/nv50-: create connectors based on nvkm info") Link: https://download.nvidia.com/open-gpu-doc/DCB/1/DCB-4.0-Specification.html#_connector_table_entry Signed-off-by: Alex Ramírez <lxrmrz732@rocketmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> [Lyude: Clarify DCB_CONNECTOR_HDMI_0 weirdness in comments] Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251213005327.9495-2-lxrmrz732@gmail.com
2026-01-21scripts/gen-btf.sh: Use CONFIG_SHELL for executionIhor Solodrai
According to the docs [1], kernel build scripts should be executed via CONFIG_SHELL, which is sh by default. Fixup gen-btf.sh to be runnable with sh, and use CONFIG_SHELL at every invocation site. See relevant discussion for context [2]. [1] https://docs.kernel.org/kbuild/makefiles.html#script-invocation [2] https://lore.kernel.org/bpf/CAADnVQ+dxmSNoJAGb6xV89ffUCKXe5CJXovXZt22nv5iYFV5mw@mail.gmail.com/ Signed-off-by: Ihor Solodrai <ihor.solodrai@linux.dev> Tested-by: Gary Guo <gary@garyguo.net> Reported-by: Gary Guo <gary@garyguo.net> Suggested-by: Thomas Weißschuh <linux@weissschuh.net> Fixes: 522397d05e7d ("resolve_btfids: Change in-place update with raw binary output") Link: https://lore.kernel.org/r/20260121181617.820300-1-ihor.solodrai@linux.dev Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2026-01-21Input: synaptics_i2c - switch to using managed resourcesDmitry Torokhov
Switch the driver to use managed resources (devm_*) which simplifier error handling and allows removing synaptics_i2c_remove() methods form the driver. Rename "ret" to "error" where makes sense while at it. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21Input: synaptics_i2c - guard polling restart in resumeMinseong Kim
synaptics_i2c_resume() restarts delayed work unconditionally, even when the input device is not opened. Guard the polling restart by taking the input device mutex and checking input_device_enabled() before re-queuing the delayed work. Fixes: eef3e4cab72ea ("Input: add driver for Synaptics I2C touchpad") Signed-off-by: Minseong Kim <ii4gsp@gmail.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260121063738.799967-1-ii4gsp@gmail.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21Input: gpio_decoder - don't use "proxy" headersAndy Shevchenko
Update header inclusions to follow IWYU (Include What You Use) principle. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113154616.3107676-6-andriy.shevchenko@linux.intel.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21Input: gpio_decoder - make use of the macros from bits.hAndy Shevchenko
Make use of BIT() where it makes sense. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113154616.3107676-5-andriy.shevchenko@linux.intel.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21Input: gpio_decoder - replace custom loop by gpiod_get_array_value_cansleep()Andy Shevchenko
There is a custom loop that repeats parts of gpiod_get_array_value_cansleep(). Use that in conjunction with bitmap API to make code shorter and easier to follow. With this done, add an upper check for amount of GPIOs given based on the driver's code. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113154616.3107676-4-andriy.shevchenko@linux.intel.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21Input: gpio_decoder - unify messages with help of dev_err_probe()Andy Shevchenko
Unify error messages that might appear during probe phase by switching to use dev_err_probe(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113154616.3107676-3-andriy.shevchenko@linux.intel.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21Input: gpio_decoder - make use of device propertiesAndy Shevchenko
Convert the module to be property provider agnostic and allow it to be used on non-OF platforms. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113154616.3107676-2-andriy.shevchenko@linux.intel.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2026-01-21drm/amdgpu: fix type for wptr in ring backupAlex Deucher
Needs to be a u64. Fixes: 77cc0da39c7c ("drm/amdgpu: track ring state associated with a fence") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 56fff1941abd3ca3b6f394979614ca7972552f7f)
2026-01-21drm/amdgpu: Fix validating flush_gpu_tlb_pasid()Timur Kristóf
When a function holds a lock and we return without unlocking it, it deadlocks the kernel. We should always unlock before returning. This commit fixes suspend/resume on SI. Tested on two Tahiti GPUs: FirePro W9000 and R9 280X. Fixes: f4db9913e4d3 ("drm/amdgpu: validate the flush_gpu_tlb_pasid()") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/202601190121.z9C0uml5-lkp@intel.com/ Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit e3a6eff92bbd960b471966d9afccb4d584546d17)
2026-01-21drm/amd/pm: Workaround SI powertune issue on Radeon 430 (v2)Timur Kristóf
Radeon 430 and 520 are OEM GPUs from 2016~2017 They have the same device id: 0x6611 and revision: 0x87 On the Radeon 430, powertune is buggy and throttles the GPU, never allowing it to reach its maximum SCLK. Work around this bug by raising the TDP limits we program to the SMC from 24W (specified by the VBIOS on Radeon 430) to 32W. Disabling powertune entirely is not a viable workaround, because it causes the Radeon 520 to heat up above 100 C, which I prefer to avoid. Additionally, revise the maximum SCLK limit. Considering the above issue, these GPUs never reached a high SCLK on Linux, and the workarounds were added before the GPUs were released, so the workaround likely didn't target these specifically. Use 780 MHz (the maximum SCLK according to the VBIOS on the Radeon 430). Note that the Radeon 520 VBIOS has a higher maximum SCLK: 905 MHz, but in practice it doesn't seem to perform better with the higher clock, only heats up more. v2: Move the workaround to si_populate_smc_tdp_limits. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 966d70f1e160bdfdecaf7ff2b3f22ad088516e9f)
2026-01-21drm/amd/pm: Don't clear SI SMC table when setting power limitTimur Kristóf
There is no reason to clear the SMC table. We also don't need to recalculate the power limit then. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit e214d626253f5b180db10dedab161b7caa41f5e9)
2026-01-21drm/amd/pm: Fix si_dpm mmCG_THERMAL_INT settingTimur Kristóf
Use WREG32 to write mmCG_THERMAL_INT. This is a direct access register. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 2555f4e4a741d31e0496572a8ab4f55941b4e30e)
2026-01-21drm/amdgpu: rename amdgpu_fence_driver_guilty_force_completion()Alex Deucher
The function no longer signals the fence so rename it to better match what it does. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu: fix type for wptr in ring backupAlex Deucher
Needs to be a u64. Fixes: 77cc0da39c7c ("drm/amdgpu: track ring state associated with a fence") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21Merge tag 'clk-meson-v6.20-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd
clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - Add support for Amlogic t7 clock controllers - Add video clocks on Amlogic s4 - HDMI PLL post divider fixes on Amlogic gx/g12 SoCs * tag 'clk-meson-v6.20-1' of https://github.com/BayLibre/clk-meson: clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro clk: meson: g12a: Limit the HDMI PLL OD to /4 clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs clk: amlogic: remove potentially unsafe flags from S4 video clocks clk: amlogic: add video-related clocks for S4 SoC dt-bindings: clock: add video clock indices for Amlogic S4 SoC clk: meson: t7: add t7 clock peripherals controller driver clk: meson: t7: add support for the T7 SoC PLL clock dt-bindings: clock: add Amlogic T7 peripherals clock controller dt-bindings: clock: add Amlogic T7 SCMI clock controller dt-bindings: clock: add Amlogic T7 PLL clock controller
2026-01-21drm/amdgpu: mark invalid records with U64_MAXGangliang Xie
set retired_page of invalid ras records to U64_MAX, and skip them when reading ras records Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu: Avoid excessive dmesg logLijo Lazar
KIQ access is not guaranteed to work reliably under all reset situations. Avoid flooding dmesg with HDP flush failure messages. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21objtool: Fix libopcodes linking with static librariesSasha Levin
Commit 436326bc525d ("objtool: fix build failure due to missing libopcodes check") tests for libopcodes using an empty main(), which passes even when static libraries lack their dependencies. This causes undefined reference errors (xmalloc, bfd_get_bits, etc.) when linking against static libopcodes without its required libbfd and libiberty. Fix by testing with an actual libopcodes symbol and trying increasingly complete library combinations until one succeeds. Fixes: 436326bc525d ("objtool: fix build failure due to missing libopcodes check") Reported-by: Rafael J. Wysocki <rafael@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Rafael J. Wysocki (Intel) <rafael@kernel.org> Link: https://patch.msgid.link/20260121162532.1596238-1-sashal@kernel.org
2026-01-21drm/amdgpu: Fix validating flush_gpu_tlb_pasid()Timur Kristóf
When a function holds a lock and we return without unlocking it, it deadlocks the kernel. We should always unlock before returning. This commit fixes suspend/resume on SI. Tested on two Tahiti GPUs: FirePro W9000 and R9 280X. Fixes: f4db9913e4d3 ("drm/amdgpu: validate the flush_gpu_tlb_pasid()") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/202601190121.z9C0uml5-lkp@intel.com/ Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: simplify svm_range_unmap_from_gpus()Yury Norov
The function calls bitmap_or() followed by for_each_set_bit(). Switch it to the dedicated for_each_or_bit() and drop the temporary bitmap. Signed-off-by: Yury Norov <ynorov@nvidia.com> Signed-off-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: Do not include VGPR MSBs in saved PC during saveLancelot Six
The current trap handler uses the top bits of ttmp1 to store a copy of sq_wave_mode.*vgpr_msb (except for src2_vgpr_msb). This is so the effective values in sq_wave_mode can be cleared to ensure correct behavior of the trap handler. When saving sq_wave_mode, the trap handler correctly rebuilds the expected value (with *vgpr_msb restored), so the save area is correct. However, the PC itself is copied from ttmp[0:1], which contains the wave's PC as well as the saved MSBs. The debugger reads the PC from the save area and is confused when non-0 values from VGPR_MSBs are present. This patch fixes this by saving the PC in the save area's PC slot, not the composite of the PC and VGPR_MSBs. On restore, the VGPR_MSBs are restored from sq_wave_mode. Signed-off-by: Lancelot Six <lancelot.six@amd.com> Tested-by: Alexey Kondratiev <Alexey.Kondratiev@amd.com> Reviewed-by: Jay Cornwall <jay.cornwall@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21Merge tag 'thead-clk-for-v6.20' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into clk-thead Pull T-HEAD clock driver updates from Drew Fustini: There is just one set of changes for thead this cycle. They add support for CPU scaling on the T-HEAD TH1520 by allowing the PLL rate used for the CPU cluster to be reconfigured. The changes have been tested in linux-next. Signed-off-by: Drew Fustini <fustini@kernel.org> * tag 'thead-clk-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: clk: thead: th1520-ap: Support CPU frequency scaling clk: thead: th1520-ap: Add macro to define multiplexers with flags clk: thead: th1520-ap: Support setting PLL rates clk: thead: th1520-ap: Add C910 bus clock clk: thead: th1520-ap: Poll for PLL lock and wait for stability dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock
2026-01-21drm/amd/pm: Correct comment above power2_cap attributesTimur Kristóf
Previously only Van Gogh supported this, but that is not true anymore since: commit 12c958d1db36 ("drm/amd/pm: Expose ppt1 limit for gc_v9_5_0") Update the comment to reflect that. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amd/pm: Return -EOPNOTSUPP when can't read power limitTimur Kristóf
So that hwmon_attributes_visible() will see that the power2_cap attributes should not be visible on GPUs that don't support the get_power_limit() function. This fixes an error when running the "sensors" command on SI. Fixes: 12c958d1db36 ("drm/amd/pm: Expose ppt1 limit for gc_v9_5_0") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amd/pm: Workaround SI powertune issue on Radeon 430 (v2)Timur Kristóf
Radeon 430 and 520 are OEM GPUs from 2016~2017 They have the same device id: 0x6611 and revision: 0x87 On the Radeon 430, powertune is buggy and throttles the GPU, never allowing it to reach its maximum SCLK. Work around this bug by raising the TDP limits we program to the SMC from 24W (specified by the VBIOS on Radeon 430) to 32W. Disabling powertune entirely is not a viable workaround, because it causes the Radeon 520 to heat up above 100 C, which I prefer to avoid. Additionally, revise the maximum SCLK limit. Considering the above issue, these GPUs never reached a high SCLK on Linux, and the workarounds were added before the GPUs were released, so the workaround likely didn't target these specifically. Use 780 MHz (the maximum SCLK according to the VBIOS on the Radeon 430). Note that the Radeon 520 VBIOS has a higher maximum SCLK: 905 MHz, but in practice it doesn't seem to perform better with the higher clock, only heats up more. v2: Move the workaround to si_populate_smc_tdp_limits. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amd/pm: Don't clear SI SMC table when setting power limitTimur Kristóf
There is no reason to clear the SMC table. We also don't need to recalculate the power limit then. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: gfx12.1 trap handler support for expert scheduling modeJay Cornwall
- Leave DEP_MODE unchanged as it is ignored in the trap handler - Save/restore SCHED_MODE (gfx12.0 saves in ttmp11) Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: gfx12.1 cluster barrier context save workaroundJay Cornwall
Trap cluster barrier may not serialize with user cluster barrier under some circumstances. Add a check for pending user cluster barrier complete. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Tested-by: Gang Ba <Gang.Ba@amd.com> Cc: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: Fix scalar load ordering in gfx12.1 trap handlerJay Cornwall
Scalar loads may arrive out-of-order with respect to KMCNT. The affected code expects the two loads to arrive in-order. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Joseph Greathouse <joseph.greathouse@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdkfd: Sync trap handler binary with sourceJay Cornwall
Binary and source desynced during branch activity. Source merge also introduced compile error. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu/vcn5.0.1: rework reset handlingJesse.Zhang
Resetting VCN resets the entire tile, including jpeg. When resetting the VCN, we need to ensure that JPEG data blocks are accessible and we also need to handle the JPEG queue. Add a helper function to restore the JPEG queue during the VCN reset. v2: split the jpeg helper in two, in the top helper we can stop the sched workqueues and attempt to wait for any outstanding fences. Then in the bottom helper, we can force completion, re-init the rings, and restart the sched workqueues (Alex) v3: merge patches 4 and 5 into one patch (Alex) Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu/vcn4.0.3: rework reset handlingJesse.Zhang
Resetting VCN resets the entire tile, including jpeg. When resetting the VCN, we need to ensure that JPEG data blocks are accessible and we also need to handle the JPEG queue. Add a helper function to restore the JPEG queue during the VCN reset. v2: split the jpeg helper in two, in the top helper we can stop the sched workqueues and attempt to wait for any outstanding fences. Then in the bottom helper, we can force completion, re-init the rings, and restart the sched workqueues (Alex) v3: merge patches 1 and 2 into one patch (Alex) Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amdgpu/vcn4.0.3: implement DPG pause mode handling for VCN 4.0.3Jesse.Zhang
For MI projects, when Dynamic Power Gating (DPG) is enabled, VCN reset operations should be performed with DPG in pause mode. Otherwise, the hardware may perform undesirable reset operations Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21drm/amd/pm: Fix si_dpm mmCG_THERMAL_INT settingTimur Kristóf
Use WREG32 to write mmCG_THERMAL_INT. This is a direct access register. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-21Merge tag 'for-6.20-clk' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra Pull Tegra clk driver updates from Thierry Reding: This series updates the Tegra clock driver to improve hardware support and code correctness. Key changes include fixing camera and display clock hierarchies for Tegra20/30 (adding CSI pad gates, reparenting DSI/CSUS), resolving a memory leak in the Tegra124 EMC driver, and optimizing system suspend/resume callbacks to remove redundant runtime PM overhead. * tag 'for-6.20-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra30: Add CSI pad clock gates clk: tegra: Set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114 clk: tegra20: Reparent dsi clock to pll_d_out0 clk: tegra: tegra124-emc: Simplify with scoped for each OF child loop clk: tegra: Adjust callbacks in tegra_clock_pm clk: tegra: tegra124-emc: Fix potential memory leak in tegra124_clk_register_emc()
2026-01-21arm64: dts: qcom: sm6115: Add CX_MEM/DBGC GPU regionsKonrad Dybcio
Describe the GPU register regions, with the former existing but not being used much if at all on this silicon, and the latter containing various debugging levers generally related to dumping the state of the IP upon a crash. Fixes: 11750af256f8 ("arm64: dts: qcom: sm6115: Add GPU nodes") Reported-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Closes: https://lore.kernel.org/linux-arm-msm/8a64f70b-8034-45e7-86a3-0015cf357132@oss.qualcomm.com/T/#m404f1425c36b61467760f058b696b8910340a063 Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251229-topic-6115_2290_gpu_dbgc-v1-3-4a24d196389c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-21arm64: dts: qcom: agatti: Add CX_MEM/DBGC GPU regionsKonrad Dybcio
Describe the GPU register regions, with the former existing but not being used much if at all on this silicon, and the latter containing various debugging levers generally related to dumping the state of the IP upon a crash. Fixes: 4faeef52c8e6 ("arm64: dts: qcom: qcm2290: Add GPU nodes") Reported-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Closes: https://lore.kernel.org/linux-arm-msm/8a64f70b-8034-45e7-86a3-0015cf357132@oss.qualcomm.com/T/#m404f1425c36b61467760f058b696b8910340a063 Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251229-topic-6115_2290_gpu_dbgc-v1-2-4a24d196389c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-21arm64: dts: qcom: sm8750: add ADSP fastrpc-compute-cb nodesAlexey Klimov
Add ADSP fastrpc nodes for sm8750 SoC. Cc: Ekansh Gupta <quic_ekangupt@quicinc.com> Cc: Srinivas Kandagatla <srini@kernel.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20251209-sm8750-fastrpc-adsp-v3-2-ccfff49a8af9@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-09 14:17:49 +0000