summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2025-11-21Merge tag 'v6.19-rockchip-dts64-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards: 9Tripod X3568, 100ASK DShanPi A1, LinkEase EasePi R1, FriendlyElec NanoPi R76S Interesting archeological addition: RK3368 (2015) gets display output afterall. New peripherals: vicap on px30 and rk356x, PCIe Gen2x1 on RK3528, use actual clock-ids for SCMI clocks - not hardcoded numbers, CQE support for the eMMC on RK3588. As well as a number of enablements for individual boards. For example enablement for the now usable NPU. * tag 'v6.19-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (43 commits) arm64: dts: rockchip: add vicap node to rk356x arm64: dts: rockchip: add the vip node to px30 arm64: dts: rockchip: fixes audio for 100ASK DshanPi A1 arm64: dts: rockchip: fixes vcc3v3_s0 supply for 100ASK DshanPi A1 arm64: dts: rockchip: fixes ethernet for 100ASK DshanPi A1 arm64: dts: rockchip: fixes regulator for 100ASK DshanPi A1 arm64: dts: rockchip: correct assigned-clock-rates spelling on 2 boards arm64: dts: rockchip: clean up devicetree for 9Tripod X3568 v4 arm64: dts: rockchip: Enable USB-C DP Alt for Indiedroid Nova arm64: dts: rockchip: add eMMC CQE support for rk3588 arm64: dts: rockchip: enable HDMI audio on Rock 5 ITX arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 3C arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 5A arm64: dts: rockchip: Move the EEPROM to correct I2C bus on Radxa ROCK 5A arm64: dts: rockchip: use SCMI clock id for gpu clock on rk356x arm64: dts: rockchip: Remove sdmmc max-frequency on RK3588S EVB1 board arm64: dts: rockchip: Remove sdmmc max-frequency for Radxa ROCK 5 ITX/5B/5B+/5T arm64: dts: rockchip: Switch microSD card detect to gpio on Radxa ROCK 5 ITX/5C arm64: dts: rockchip: Add devicetree for the 9Tripod X3568 v4 dt-bindings: arm: rockchip: Add 9Tripod X3568 series ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'v6.19-rockchip-dts32-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt A number of cleanups for older socs. * tag 'v6.19-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: move edp assigned-clocks to edp node on rk3288 ARM: dts: rockchip: Add spi_flash label to rk3288-veyron ARM: dts: rockchip: Remove mshc aliases from RK3288 ARM: dts: rockchip: Adapt tps65910 nodes on RK3066 boards Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21workqueue: Don't rely on wq->rescuer to stop rescuerLai Jiangshan
The commit1 def98c84b6cd ("workqueue: Fix spurious sanity check failures in destroy_workqueue()") tries to fix spurious sanity check failures by stopping send_mayday() via setting wq->rescuer to NULL. But it fails to stop the pwq->mayday_node requeuing in the rescuer, and the commit2 e66b39af00f4 ("workqueue: Fix pwq ref leak in rescuer_thread()") fixes it by checking wq->rescuer which is the result of commit1. Both commits together really fix spurious sanity check failures caused by the rescuer, but they both use a convoluted method by relying on wq->rescuer state rather than the real count of work items. Actually __WQ_DESTROYING and drain_workqueue() together already stop send_mayday() by draining all the work items and ensuring no new work item requeuing. And the more proper fix to stop the pwq->mayday_node requeuing in the rescuer is from commit3 4f3f4cf388f8 ("workqueue: avoid unneeded requeuing the pwq in rescuer thread") and renders the checking of wq->rescuer in commit2 unnecessary. So __WQ_DESTROYING, drain_workqueue() and commit3 together fix spurious sanity check failures introduced by the rescuer. Just remove the convoluted code of using wq->rescuer. Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2025-11-21workqueue: Only assign rescuer work when really neededLai Jiangshan
If the pwq does not need rescue (normal workers have been created or become available), the rescuer can immediately move on to other stalled pwqs. Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2025-11-21workqueue: Factor out assign_rescuer_work()Lai Jiangshan
Move the code to assign work to rescuer and assign_rescuer_work(). Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2025-11-21x86/mce: Handle AMD threshold interrupt stormsSmita Koralahalli
Extend the logic of handling CMCI storms to AMD threshold interrupts. Rely on the similar approach as of Intel's CMCI to mitigate storms per CPU and per bank. But, unlike CMCI, do not set thresholds and reduce interrupt rate on a storm. Rather, disable the interrupt on the corresponding CPU and bank. Re-enable back the interrupts if enough consecutive polls of the bank show no corrected errors (30, as programmed by Intel). Turning off the threshold interrupts would be a better solution on AMD systems as other error severities will still be handled even if the threshold interrupts are disabled. [ Tony: Small tweak because mce_handle_storm() isn't a pointer now ] [ Yazen: Rebase and simplify ] [ Avadhut: Remove check to not clear bank's bit in mce_poll_banks and fix checkpatch warnings. ] Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Avadhut Naik <avadhut.naik@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20251121190542.2447913-3-avadhut.naik@amd.com
2025-11-21iommufd/iommufd_private.h: Avoid -Wflex-array-member-not-at-end warningGustavo A. R. Silva
-Wflex-array-member-not-at-end was introduced in GCC-14, and we are getting ready to enable it, globally. Move the conflicting declaration to the end of the corresponding structure. Notice that struct iommufd_vevent is a flexible structure, this is a structure that contains a flexible-array member. Fix the following warning: drivers/iommu/iommufd/iommufd_private.h:621:31: warning: structure containing a flexible array member is not at the end of another structure [-Wflex-array-member-not-at-end] Link: https://patch.msgid.link/r/aRHOAwpATIE0oajj@kspp Signed-off-by: "Gustavo A. R. Silva" <gustavoars@kernel.org> Fixes: e36ba5ab808e ("iommufd: Add IOMMUFD_OBJ_VEVENTQ and IOMMUFD_CMD_VEVENTQ_ALLOC") Reviewed-by: Kevin Tian <kevin.tian@intel.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2025-11-21iommufd/driver: Fix counter initialization for counted_by annotationGustavo A. R. Silva
One of the requirements for counted_by annotations is that the counter member must be initialized before the first reference to the flexible-array member. Move the vevent->data_len = data_len; initialization to before the first access to flexible array vevent->event_data. Link: https://patch.msgid.link/r/aRL7ZFFqM5bRTd2D@kspp Cc: stable@vger.kernel.org Fixes: e8e1ef9b77a7 ("iommufd/viommu: Add iommufd_viommu_report_event helper") Signed-off-by: "Gustavo A. R. Silva" <gustavoars@kernel.org> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2025-11-21x86/mce: Do not clear bank's poll bit in mce_poll_banks on AMD SMCA systemsAvadhut Naik
Currently, when a CMCI storm detected on a Machine Check bank, subsides, the bank's corresponding bit in the mce_poll_banks per-CPU variable is cleared unconditionally by cmci_storm_end(). On AMD SMCA systems, this essentially disables polling on that particular bank on that CPU. Consequently, any subsequent correctable errors or storms will not be logged. Since AMD SMCA systems allow banks to be managed by both polling and interrupts, the polling banks bitmap for a CPU, i.e., mce_poll_banks, should not be modified when a storm subsides. Fixes: 7eae17c4add5 ("x86/mce: Add per-bank CMCI storm mitigation") Signed-off-by: Avadhut Naik <avadhut.naik@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20251121190542.2447913-2-avadhut.naik@amd.com
2025-11-22samples: rust: fix module name for Rust PCI driver samplePeter Colberg
Replace driver_pci -> rust_driver_pci in config SAMPLE_RUST_DRIVER_PCI. Signed-off-by: Peter Colberg <pcolberg@redhat.com> Fixes: 685376d18e9a ("samples: rust: add Rust PCI sample driver") Link: https://patch.msgid.link/20251120-rust-driver-pci-fix-module-name-v1-1-430cee310dc0@redhat.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-11-21hwmon: (aspeed-g6-pwm-tach): Add AST2700 compatible stringBilly Tsai
Extends device tree support to include the AST2700 chip variant by adding its compatible string to the device match table. The AST2700 PWM/TACH hardware is compatible with the existing driver implementation used for AST2600. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20251120-upstream_pwm_tach-v3-2-eaa2f9b300a2@aspeedtech.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2025-11-21dt-bindings: hwmon: Add AST2700 compatibleBilly Tsai
Adds support for the AST2700 PWM/Tach controller by extending the compatible string enumeration in the device tree binding. The AST2700 PWM/Tach hardware is compatible with the existing binding schema and requires no additional properties or modifications beyond the new compatible string. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20251120-upstream_pwm_tach-v3-1-eaa2f9b300a2@aspeedtech.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2025-11-21hwmon: (asus-ec-sensors) add ROG STRIX X470-I GAMINGRené Rebe
Add support for ROG STRIX X470-I GAMING Signed-off-by: René Rebe <rene@exactco.de> Reviewed-by: Eugene Shalygin <eugene.shalygin@gmail.com> Link: https://lore.kernel.org/r/20251120.140009.210830394703243387.rene@exactco.de Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2025-11-21Merge tag 'loongarch-fixes-6.18-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson Pull LoongArch fixes from Huacai Chen: "Use UAPI types in ptrace UAPI header to fix nolibc ptrace. Fix CPU name display, NUMA node parsing, kexec/kdump, PCI init and BPF trampoline" * tag 'loongarch-fixes-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: LoongArch: BPF: Disable trampoline for kernel module function trace LoongArch: Don't panic if no valid cache info for PCI LoongArch: Mask all interrupts during kexec/kdump LoongArch: Fix NUMA node parsing with numa_memblks LoongArch: Consolidate CPU names in /proc/cpuinfo LoongArch: Use UAPI types in ptrace UAPI header
2025-11-21Merge tag 'v6.18-rc6-smb3-client-fixes' of git://git.samba.org/sfrench/cifs-2.6Linus Torvalds
Pull smb client fixes from Steve French: - Fix potential memory leak in mount - Add some missing read tracepoints - Fix locking issue with directory leases * tag 'v6.18-rc6-smb3-client-fixes' of git://git.samba.org/sfrench/cifs-2.6: cifs: Add the smb3_read_* tracepoints to SMB1 cifs: fix memory leak in smb3_fs_context_parse_param error path smb: client: introduce close_cached_dir_locked()
2025-11-21Merge tag 'io_uring-6.18-20251120' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux Pull io_uring fix from Jens Axboe: "Just a single fix for a mixup of arguments for the skb_queue_splice() call, in the io_uring timestamp retrieval code" * tag 'io_uring-6.18-20251120' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux: io_uring/cmd_net: fix wrong argument types for skb_queue_splice()
2025-11-21Merge tag 'block-6.18-20251120' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux Pull block fixes from Jens Axboe: "NVMe pull request via Keith: - Admin queue use-after-free fix (Keith) - Target authentication fix (Alistar) - Multipath lockdeup fix (Shin'ichiro) - FC transport teardown fixes (Ewan)" * tag 'block-6.18-20251120' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux: nvme: nvme-fc: Ensure ->ioerr_work is cancelled in nvme_fc_delete_ctrl() nvme: nvme-fc: move tagset removal to nvme_fc_delete_ctrl() nvme-multipath: fix lockdep WARN due to partition scan work nvmet-auth: update sc_c in target host hash calculation nvme: fix admin request_queue lifetime
2025-11-21Merge tag 'ata-6.18-rc7' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux Pull ata fixes from Niklas Cassel: - Add a missing refcount decrement in ata_scsi_dev_rescan() when the device or its queue is not running. In the case where the device is running, the recount is already decremented properly (Yihang Li) - Generate the proper sense code for a Security locked device. There was a regression caused by a recent change of how sense data is generated for commands that did not provide any sense data. This broke system suspend for Security locked devices. Generate the sense data that the SCSI disk driver expects for a Security locked device so that system suspend works again (me) - Set capacity to zero for a Security locked device. All I/O commands will be aborted by a Security locked device. Thus, the block layer disk partition scanning will result in a bunch of, for the user, confusing I/O errors in dmesg during boot. Since a Security locked device is unusable anyway, set the capacity to zero, to avoid the disk partition scanning during boot. We still create the block device in /dev such that the user may unlock the device using e.g. hdparm (me) * tag 'ata-6.18-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux: ata: libata-core: Set capacity to zero for a security locked drive ata: libata-scsi: Fix system suspend for a security locked drive ata: libata-scsi: Add missing scsi_device_put() in ata_scsi_dev_rescan()
2025-11-21drm/i915/cx0: Read out power-down state of both PHY lanes for reversed lanesImre Deak
For a port used with lane reversal enabled the first two TX lanes will be enabled in PHY lane#1 instead of PHY lane#0. At the moment the HW readout will read out the power-down state for these two TX lanes from PHY lane#0 incorrectly. The display HW lane reversal feature (vs. the similar TCSS lane swap) is only used for TypeC legacy mode and for non-TypeC PHYs. Since in both of these cases the display owns both PHY lanes, both of these PHY lanes' state can be read out. Do that to fix cases when lane reversal is used with 1 or 2 active TX lanes. While at it add an assert to the PLL enable function about the above assumption on when lane reversal can be used. Cc: Mika Kahola <mika.kahola@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Fixes: 230d4c748113 ("drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state") Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251120172358.1282765-5-imre.deak@intel.com
2025-11-21drm/i915/cx0: Read out power-down state of both TXs in PHY lane 0Imre Deak
If the number of used lanes is 1 or 2 then the power-down state of both TX lanes in PHY lane 0 should be read out. If 1 lane is used only 1 TX lane will be checked, make sure both TXs are checked in this case. Cc: Mika Kahola <mika.kahola@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Fixes: 230d4c748113 ("drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state") Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251120172358.1282765-4-imre.deak@intel.com
2025-11-21drm/i915/cx0: Use intel_port_to_tc() instead of open coding itImre Deak
Use intel_port_to_tc() in mtl_port_to_pll_id(), instead of open coding the same. v2: s/USe/Use in commit message. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251120172358.1282765-3-imre.deak@intel.com
2025-11-21drm/i915/tc: Add separate intel_tc_phy_port_to_tc() for TC DDI/PHY portsImre Deak
intel_port_to_tc() returns the PORT_TC1..6 -> TC_PORT_1..6 mapping only for DDI ports that are connected to a TypeC PHY. In some cases this mapping is also required for TypeC DDI ports which are not connected to a TypeC PHY. Such DDI ports are the PORT_TC1..4 ports on RKL/ADLS/BMG. Add a separate intel_tc_phy_to_tc() helper to return the mapping for ports connected to a TypeC PHY, and make all the current users - which expect this semantic - call this helper. A follow-up change will need to get the same mapping for TypeC DDI ports not connected to a TypeC PHY, leave intel_port_to_tc() exported for that. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251120172358.1282765-2-imre.deak@intel.com
2025-11-21drm/i915/cx0: Fix port to PLL ID mapping on BMGImre Deak
The intel_port_to_tc() call in mtl_port_to_pll_id() assumed that all TypeC DDI ports are connected to a TypeC PHY. This is not true on BMG where all the ports - including the PORT_TC1..4 TypeC DDI ports - are connected to a non-TypeC PHY. For these ports intel_port_to_tc() returns TC_PORT_NONE, which results in an incorrect port -> PLL ID mapping. Fix this up by using the expected PORT_TC1..4 port -> TC_PORT_1..4 tc_port mapping on BMG as well. Fixes: ca1eda5cd476c ("drm/i915/cx0: Add MTL+ .get_dplls hook") Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251120172358.1282765-1-imre.deak@intel.com
2025-11-21Merge tag 'pinctrl-v6.18-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: - Fix register naming in the Mediatek mt8189 driver - Select REGMAP_MMIO for the Realtek RTD driver - Fix the number of items in groups in the Toshiba Visconti driver - Fix a memory leak in the Cirrus CS42L43 driver - Fix a deadlock (!) in Qualcomm pinmux configuration - Fix use of uninitialized memory and list initialization in the S32CC pin controller * tag 'pinctrl-v6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: dt-bindings: pinctrl: xlnx,versal-pinctrl: Add missing unevaluatedProperties on '^conf' nodes pinctrl: s32cc: initialize gpio_pin_config::list after kmalloc() pinctrl: s32cc: fix uninitialized memory in s32_pinctrl_desc pinctrl: qcom: msm: Fix deadlock in pinmux configuration pinctrl: cirrus: Fix fwnode leak in cs42l43_pin_probe() dt-bindings: pinctrl: toshiba,visconti: Fix number of items in groups pinctrl: realtek: Select REGMAP_MMIO for RTD driver pinctrl: mediatek: mt8189: align register base names to dt-bindings ones pinctrl: mediatek: mt8196: align register base names to dt-bindings ones
2025-11-21Merge branch 'selftests-bpf-networking-test-cleanups'Martin KaFai Lau
Hoyeon Lee says: ==================== selftests/bpf: networking test cleanups This series finishes the sockaddr_storage migration in the networking selftests by removing the remaining open-coded IPv4/IPv6 wrappers (addr_port/tuple in cls_redirect, sa46 in select_reuseport). The tests now use sockaddr_storage directly. No other custom socket-address wrappers remain after this series, so the churn stops here and behavior is unchanged. ==================== Link: https://patch.msgid.link/20251121081332.2309838-1-hoyeon.lee@suse.com Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
2025-11-21selftests/bpf: Use sockaddr_storage instead of sa46 in select_reuseport testHoyeon Lee
The select_reuseport selftest uses a custom sa46 union to represent IPv4 and IPv6 addresses. This custom wrapper requires extra manual handling for address family and field extraction. Replace sa46 with sockaddr_storage and update the helper functions to operate on native socket structures. This simplifies the code and removes unnecessary custom address-handling logic. No functional changes intended. Reviewed-by: Amery Hung <ameryhung@gmail.com> Signed-off-by: Hoyeon Lee <hoyeon.lee@suse.com> Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org> Link: https://patch.msgid.link/20251121081332.2309838-3-hoyeon.lee@suse.com
2025-11-21selftests/bpf: Use sockaddr_storage directly in cls_redirect testHoyeon Lee
The cls_redirect test uses a custom addr_port/tuple wrapper to represent IPv4/IPv6 addresses and ports. This custom wrapper requires extra conversion logic and specific helpers such as fill_addr_port(), which are no longer necessary when using standard socket address structures. This commit replaces addr_port/tuple with the standard sockaddr_storage so test handles address families and ports using native socket types. It removes the custom helper, eliminates redundant casts, and simplifies the setup helpers without functional changes. set_up_conn() and build_input() now take src/dst sockaddr_storage directly. Reviewed-by: Amery Hung <ameryhung@gmail.com> Signed-off-by: Hoyeon Lee <hoyeon.lee@suse.com> Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org> Link: https://patch.msgid.link/20251121081332.2309838-2-hoyeon.lee@suse.com
2025-11-21Merge tag 'gpio-fixes-for-v6.18-rc7' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio fixes from Bartosz Golaszewski: - fix a use-after-free bug in GPIO character device code - update MAINTAINERS * tag 'gpio-fixes-for-v6.18-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: MAINTAINERS: update my email address gpio: cdev: make sure the cdev fd is still active before emitting events
2025-11-21MAINTAINERS: refer to intended file in STANDALONE CACHE CONTROLLER DRIVERSLukas Bulwahn
Commit 23db6eed72bd ("MAINTAINERS: Add Jonathan Cameron to drivers/cache and add lib/cache_maint.c + header") intends to add a file entry pointing to the cache_coherency.h file, but messes up to name the right path. Update the entry to the intended file. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-21cache: Support cache maintenance for HiSilicon SoC Hydra Home AgentYushan Wang
Hydra Home Agent is a device used to maintain cache coherency. Add support for explicit cache maintenance operations using it. A system has multiple of these agents. Whilst only one agent is responsible for a given cache line, interleave means that for a range operation, responsibility for the cache lines making up the range will typically be spread across multiple instances. Put this driver on a new Kconfig menu under drivers/cache. The short description as memory hotplug like operations is intended to cover the somewhat complex set of cases where this unit applies and differentiate it clearly from typical non coherent DMA flows. Co-developed-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Yushan Wang <wangyushan12@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-21cache: Make top level Kconfig menu a boolean dependent on RISCVJonathan Cameron
The next patch will add a new type of cache maintenance driver responsible for flushing deeper than is necessary for non coherent DMA (current use case of drivers/cache drivers), as needed when performing operations such as memory hotplug and security unlocking of persistent memory. The two types of operation are similar enough to share a drivers/cache directory and MAINTAINERS but are otherwise currently unrelated. To avoid confusion have two separate menus. Each has dependencies that are implemented by making them boolean symbols, here CACHEMAINT_FOR_DMA which is dependent on RISCV as all driver are currently for platforms of that architecture. Set new symbol default to y to avoid breaking existing configs. This has no affect on actual code built, just visibility of the menu. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-21MAINTAINERS: Add Jonathan Cameron to drivers/cache and add lib/cache_maint.c ↵Jonathan Cameron
+ header Seems unfair to inflict the cache-coherency drivers on Conor with out also stepping up as a second maintainer for drivers/cache. Include the library support for cache-coherency maintenance drivers to the existing entry. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-21arm64: Select GENERIC_CPU_CACHE_MAINTENANCEJonathan Cameron
The generic CPU cache maintenance framework provides a way to register drivers for devices implementing the underlying support for cpu_cache_has_invalidate_memregion(). Enable it for arm64 by selecting GENERIC_CPU_CACHE_MAINTENANCE which provides the implementation for, and in turn selects, ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-21lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGIONYicong Yang
ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION provides the mechanism for invalidating certain memory regions in a cache-incoherent manner. Currently this is used by NVDIMM and CXL memory drivers in cases where it is necessary to flush all data from caches by physical address range. The operations in question are effectively memory hotplug, where stale data might otherwise remain in the caches. This is separate from the invalidates done to enable use of non-coherent DMA masters, primarily in terms of when it is needed (not related to DMA mappings) and how deep the flush must push data. The flushes done for non-coherent DMA only need to reach the Point of Coherence of a single host (which is often nearer CPUs and DMA masters than the physical storage). This operation must push the data out of non architectural caches (memory-side caches, write buffers etc) and typically all the way to the memory device. In some architectures these operations are supported by system components that may become available only later in boot as they are either present on a discoverable bus, or via a firmware description of an MMIO interface (e.g. ACPI DSDT). Provide a framework to handle this case. Architectures can opt in for this support via CONFIG_GENERIC_CPU_CACHE_MAINTENANCE Add a registration framework. Each driver provides an ops structure and the first op is Write Back and Invalidate by PA Range. The driver may over invalidate. For systems that can perform this operation asynchronously an optional completion check operation is also provided. If present that must be called to ensure that the action has finished. This provides a considerable performance advantage if multiple agents are involved in the maintenance operation. When multiple agents are present in the system each should register with this framework and the core code will issue the invalidate to all of them before checking for completion on each. This is done to avoid need for filtering in the core code which can become complex when interleave, potentially across different cache coherency hardware is going on, so it is easier to tell everyone and let those who don't care do nothing. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-21lib/crypto: tests: Fix KMSAN warning in test_sha256_finup_2x()Eric Biggers
Fully initialize *ctx, including the buf field which sha256_init() doesn't initialize, to avoid a KMSAN warning when comparing *ctx to orig_ctx. This KMSAN warning slipped in while KMSAN was not working reliably due to a stackdepot bug, which has now been fixed. Fixes: 6733968be7cb ("lib/crypto: tests: Add tests and benchmark for sha256_finup_2x()") Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251121033431.34406-1-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-11-21EDAC/igen6: Fix error handling in igen6_edac driverMa Ke
The igen6_edac driver calls device_initialize() for all memory controllers in igen6_register_mci(), but misses corresponding put_device() calls in error paths and during normal shutdown in igen6_unregister_mcis(). Adding the missing put_device() calls improves code readability and ensures proper reference counting for the device structure. Found by code review. Signed-off-by: Ma Ke <make24@iscas.ac.cn> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20251105090244.23327-1-make24@iscas.ac.cn
2025-11-21EDAC/imh: Setup 'imh_test' debugfs testing nodeQiuxu Zhuo
Setup the following debugfs testing node to enable fake memory error address decoding tests for the imh_edac driver. /sys/kernel/debug/edac/imh_test/addr Tested-by: Yi Lai <yi1.lai@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20251119134132.2389472-8-qiuxu.zhuo@intel.com
2025-11-21EDAC/{skx_comm,imh}: Detect 2-level memory configurationQiuxu Zhuo
Detect 2-level memory configurations and notify the 'skx_common' library to enable ADXL 2-level memory error decoding. Tested-by: Yi Lai <yi1.lai@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20251119134132.2389472-7-qiuxu.zhuo@intel.com
2025-11-21EDAC/skx_common: Extend the maximum number of DRAM chip row bitsQiuxu Zhuo
The allowed maximum number of row bits for DRAM chips in the Diamond Rapids server processor is up to 19. Extend the current maximum row bits from 18 to 19. Tested-by: Yi Lai <yi1.lai@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20251119134132.2389472-6-qiuxu.zhuo@intel.com
2025-11-21EDAC/{skx_common,imh}: Add EDAC driver for Intel Diamond Rapids serversQiuxu Zhuo
Intel Diamond Rapids CPUs include Integrated Memory and I/O Hubs (IMH). The memory controllers within the IMHs provide memory stacks to the processor. Create a new driver for this IMH-based memory controllers rather than applying additional patches to the existing i10nm_edac.c for the following reasons: 1) The memory controllers are not presented as PCI devices; instead, the detection and all their registers have been transitioned to MMIO-based memory spaces. 2) Validation processes are costly. Modifications to i10nm_edac would require extensive validation checks against multiple platforms, including Ice Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Sierra Forest, and Grand Ridge. 3) Future Intel CPUs will likely only need patches on top of this new EDAC driver. Validation can be limited to Diamond Rapids servers and future Intel CPU generations. [Tony: Fix kerneldoc for struct local_reg] [randconfig: Added dependencies on NFIT and DMI] Tested-by: Yi Lai <yi1.lai@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20251119134132.2389472-5-qiuxu.zhuo@intel.com
2025-11-21KVM: selftests: Make sure vm->vpages_mapped is always up-to-dateYosry Ahmed
Call paths leading to __virt_pg_map() are currently: (a) virt_pg_map() -> virt_arch_pg_map() -> __virt_pg_map() (b) virt_map_level() -> __virt_pg_map() For (a), calls to virt_pg_map() from kvm_util.c make sure they update vm->vpages_mapped, but other callers do not. Move the sparsebit_set() call into virt_pg_map() to make sure all callers are captured. For (b), call sparsebit_set_num() from virt_map_level(). It's tempting to have a single the call inside __virt_pg_map(), however: - The call path in (a) is not x86-specific, while (b) is. Moving the call into __virt_pg_map() would require doing something similar for other archs implementing virt_pg_map(). - Future changes will reusue __virt_pg_map() for nested PTEs, which should not update vm->vpages_mapped, i.e. a triple underscore version that does not update vm->vpages_mapped would need to be provided. Signed-off-by: Yosry Ahmed <yosry.ahmed@linux.dev> Link: https://patch.msgid.link/20251021074736.1324328-12-yosry.ahmed@linux.dev Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-11-21KVM: selftests: Stop using __virt_pg_map() directly in testsYosry Ahmed
Replace __virt_pg_map() calls in tests by high-level equivalent functions, removing some loops in the process. No functional change intended. Signed-off-by: Yosry Ahmed <yosry.ahmed@linux.dev> Link: https://patch.msgid.link/20251021074736.1324328-11-yosry.ahmed@linux.dev Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-11-21Merge tag 'drm-fixes-2025-11-21' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds
Pull drm fixes from Dave Airlie: "A range of small fixes across the board, the i915 display disambiguation is probably the biggest otherwise amdgpu and xe as usual with tegra, nouveau, radeon and a core atomic fix. Looks mostly normal. atomic: - Return error codes on failed blob creation for planes nouveau: - Fix memory leak tegra: - Fix device ref counting - Fix pid ref counting - Revert booting on Pixel C xe: - Fix out-of-bounds access with BIT() - Fix kunit test checking wrong condition - Drop duplicate kconfig select - Fix guc2host irq handler with MSI-X i915: - Wildcat Lake and Panther Lake detangled for display fixes amdgpu: - DTBCLK gating fix - EDID fetching retry improvements - HDMI HPD debounce filtering - DCN 2.0 cursor fix - DP MST PBN fix - VPE fix - GC 11 fix - PRT fix - MMIO remap page fix - SR-IOV fix radeon: - Fence deadlock fix" * tag 'drm-fixes-2025-11-21' of https://gitlab.freedesktop.org/drm/kernel: (25 commits) drm/amdgpu: Add sriov vf check for VCN per queue reset support. drm/amdgpu/ttm: Fix crash when handling MMIO_REMAP in PDE flags drm/amdgpu/vm: Check PRT uAPI flag instead of PTE flag drm/amdgpu: Skip emit de meta data on gfx11 with rs64 enabled drm/amd: Skip power ungate during suspend for VPE drm/plane: Fix create_in_format_blob() return value drm/xe/irq: Handle msix vector0 interrupt drm/xe: Remove duplicate DRM_EXEC selection from Kconfig drm/xe/kunit: Fix forcewake assertion in mocs test drm/xe: Prevent BIT() overflow when handling invalid prefetch region drm/radeon: delete radeon_fence_process in is_signaled, no deadlock drm/amd/display: Fix pbn to kbps Conversion drm/amd/display: Clear the CUR_ENABLE register on DCN20 on DPP5 drm/amd/display: Add an HPD filter for HDMI drm/amd/display: Increase DPCD read retries drm/amd/display: Move sleep into each retry for retrieve_link_cap() drm/amd/display: Prevent Gating DTBCLK before It Is Properly Latched drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY A drm/i915/display: Add definition for wcl as subplatform drm/pcids: Split PTL pciids group to make wcl subplatform ...
2025-11-21Merge branch 'mauro' into docs-mwJonathan Corbet
Mauro says: That's the final series to complete the migration of documentation build: it converts get_feat from Perl to Python. V2 is technically identical to v1: the only difference is that it now uses tools/lib/python/feat to store the library logic. With that, no Sphinx in-kernel extensions use fork anymore to call ancillary scripts: everything is now importing Python methods directly from the libraries. There's nothing special on this conversion: it is a direct translation, almost bug-compatible with the original version (*). (*) I did solve two or three caveats on patch 1. Most of the complexity of the script relies at the logic to produce ReST tables. I do have here on my internal scripts a (somewhat) generic formatter for ReST tables in Python. I was tempted to convert the logic to use it, but, as this could cause regressions, I opted to not do it right now, mainly because the matrix table logic is complex. Also, I'm tempted to modify a little bit the output there, but extra tests are required to see if PDF output would work with complex tables (I remember I had a problem with that in the past). So, I'm postponing such extra cleanup.
2025-11-21get_feat.pl: remove it, as it got replaced by get_feat.pyMauro Carvalho Chehab
Now that this was rewritten in Python, we can remove the old tool. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <1f53e0fa48616af189ce98b45a65cc0c245e7aaf.1763492868.git.mchehab+huawei@kernel.org>
2025-11-21Documentation/sphinx/kernel_feat.py: use class directlyMauro Carvalho Chehab
Now that get_feat is in Python, we don't need to use subprocess to fork an executable file: we can use the feature classes directly. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <c59d2542d7cc914fd5f8c84df966e63adc924cdc.1763492868.git.mchehab+huawei@kernel.org>
2025-11-21tools/docs/get_feat.py: convert get_feat.pl to PythonMauro Carvalho Chehab
As we want to call Python code directly at the Sphinx extension, convert get_feat.pl to Python. The code was made to be (almost) bug-compatible with the Perl version, with two exceptions: 1. Currently, Perl script outputs a wrong table if arch is set to a non-existing value; 2. the ReST table output when --feat is used without --arch has an invalid format, as the number of characters for the table delimiters are wrong. Those two bugs were fixed while testing the conversion. Additionally, another caveat was solved: the output when --feat is used without arch and the feature doesn't exist doesn't contain an empty table anymore. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <03c26cee1ec567804735a33047e625ef5ab7bfa8.1763492868.git.mchehab+huawei@kernel.org>
2025-11-21serial: 8250_platform: simplify IRQF_SHARED handlingJiri Slaby (SUSE)
IRQF_SHARED is the only flag handled in __serial8250_isa_init_ports() and serial8250_probe_platform(). There is no need to precompute the flags. Instead, initialize port->irqflags directly in the for loop. Note the "if (bool)" is cheap and these are not hot paths anyway. Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Link: https://patch.msgid.link/20251119092457.826789-7-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-11-21serial: 8250: make share_irqs local to 8250_platformJiri Slaby (SUSE)
share_irqs is used solely in 8250_platform. Make it local to that file. Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Link: https://patch.msgid.link/20251119092457.826789-6-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-11-21serial: 8250: move skip_txen_test to coreJiri Slaby (SUSE)
8250_core is the only place where skip_txen_test is used. And platform and core end up in 8250.ko, so there is no change in module name (param prefix). Therefore, move skip_txen_test there and make it local. Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Link: https://patch.msgid.link/20251119092457.826789-5-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-11 20:40:49 +0000