linux.git/virt/kvm/arm/hyp, branch v4.9

arm64: KVM: Move vgic-v3 save/restore to virt/kvm/arm/hyp

2016-09-22T11:21:46+00:00

So we can reuse the code under arch/arm

Signed-off-by: Vladimir Murzin 
Acked-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

arm64: KVM: Inject a vSerror if detecting a bad GICV access at EL2

2016-09-08T10:53:00+00:00

If, when proxying a GICV access at EL2, we detect that the guest is
doing something silly, report an EL1 SError instead ofgnoring the
access.

Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

arm64: KVM: vgic-v2: Add GICV access from HYP

2016-09-08T10:53:00+00:00

Now that we have the necessary infrastructure to handle MMIO accesses
in HYP, perform the GICV access on behalf of the guest. This requires
checking that the access is strictly 32bit, properly aligned, and
falls within the expected range.

When all condition are satisfied, we perform the access and tell
the rest of the HYP code that the instruction has been correctly
emulated.

Reviewed-by: Christoffer Dall 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

arm64: KVM: vgic-v2: Add the GICV emulation infrastructure

2016-09-08T10:53:00+00:00

In order to efficiently perform the GICV access on behalf of the
guest, we need to be able to avoid going back all the way to
the host kernel.

For this, we introduce a new hook in the world switch code,
conveniently placed just after populating the fault info.
At that point, we only have saved/restored the GP registers,
and we can quickly perform all the required checks (data abort,
translation fault, valid faulting syndrome, not an external
abort, not a PTW).

Coming back from the emulation code, we need to skip the emulated
instruction. This involves an additional bit of save/restore in
order to be able to access the guest's PC (and possibly CPSR if
this is a 32bit guest).

At this stage, no emulation code is provided.

Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: The GIC is dead, long live the GIC

2016-07-03T21:09:37+00:00

I don't think any single piece of the KVM/ARM code ever generated
as much hatred as the GIC emulation.

It was written by someone who had zero experience in modeling
hardware (me), was riddled with design flaws, should have been
scrapped and rewritten from scratch long before having a remote
chance of reaching mainline, and yet we supported it for a good
three years. No need to mention the names of those who suffered,
the git log is singing their praises.

Thankfully, we now have a much more maintainable implementation,
and we can safely put the grumpy old GIC to rest.

Fellow hackers, please raise your glass in memory of the GIC:

	The GIC is dead, long live the GIC!

Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: vgic-v2: Clear all dirty LRs

2016-05-31T14:09:28+00:00

When saving the state of the list registers, it is critical to
reset them zero, as we could otherwise leave unexpected EOI
interrupts pending for virtual level interrupts.

Cc: stable@vger.kernel.org # v4.6+
Signed-off-by: Christoffer Dall 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: vgic-new: enable build

2016-05-20T13:40:09+00:00

Now that the new VGIC implementation has reached feature parity with
the old one, add the new files to the build system and add a Kconfig
option to switch between the two versions.
We set the default to the new version to get maximum test coverage,
in case people experience problems they can switch back to the old
behaviour if needed.

Signed-off-by: Andre Przywara 
Acked-by: Christoffer Dall

KVM: arm/arm64: Get rid of vgic_cpu->nr_lr

2016-05-20T13:39:41+00:00

The number of list registers is a property of the underlying system, not
of emulated VGIC CPU interface.

As we are about to move this variable to global state in the new vgic
for clarity, move it from the legacy implementation as well to make the
merge of the new code easier.

Signed-off-by: Christoffer Dall 
Signed-off-by: Andre Przywara 
Reviewed-by: Andre Przywara

KVM: arm/arm64: Move timer IRQ map to latest possible time

2016-05-20T13:39:41+00:00

We are about to modify the VGIC to allocate all data structures
dynamically and store mapped IRQ information on a per-IRQ struct, which
is indeed allocated dynamically at init time.

Therefore, we cannot record the mapped IRQ info from the timer at timer
reset time like it's done now, because VCPU reset happens before timer
init.

A possible later time to do this is on the first run of a per VCPU, it
just requires us to move the enable state to be a per-VCPU state and do
the lookup of the physical IRQ number when we are about to run the VCPU.

Signed-off-by: Christoffer Dall 
Signed-off-by: Andre Przywara

KVM: arm/arm64: vgic-v2: Only wipe LRs on vcpu exit

2016-03-09T04:23:56+00:00

So far, we're always writing all possible LRs, setting the empty
ones with a zero value. This is obvious doing a lot of work for
nothing, and we're better off clearing those we've actually
dirtied on the exit path (it is very rare to inject more than one
interrupt at a time anyway).

Reviewed-by: Christoffer Dall 
Signed-off-by: Marc Zyngier