linux.git/virt/kvm/arm/hyp, branch v4.13

arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1

2017-06-15T08:45:07+00:00

Per ARM DDI 0487B.a, the registers are named ICC_IGRPEN*_EL1 rather than
ICC_GRPEN*_EL1. Correct our mnemonics and comments to match, before we
add more GICv3 register definitions.

Signed-off-by: Mark Rutland 
Cc: Catalin Marinas 
Cc: Marc Zyngier 
Cc: kvmarm@lists.cs.columbia.edu
Acked-by: Christoffer Dall 
Acked-by: Will Deacon 
Signed-off-by: Christoffer Dall

KVM: arm64: Log an error if trapping a write-to-read-only GICv3 access

2017-06-15T08:45:07+00:00

A write-to-read-only GICv3 access should UNDEF at EL1. But since
we're in complete paranoia-land with broken CPUs, let's assume the
worse and gracefully handle the case.

Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Signed-off-by: Christoffer Dall

KVM: arm64: Log an error if trapping a read-from-write-only GICv3 access

2017-06-15T08:45:06+00:00

A read-from-write-only GICv3 access should UNDEF at EL1. But since
we're in complete paranoia-land with broken CPUs, let's assume the
worse and gracefully handle the case.

Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_PMR_EL1 handler

2017-06-15T08:45:05+00:00

Add a handler for reading/writing the guest's view of the ICC_PMR_EL1
register, which is located in the ICH_VMCR_EL2.VPMR field.

Tested-by: Alexander Graf 
Acked-by: David Daney 
Acked-by: Christoffer Dall 
Reviewed-by: Eric Auger 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_CTLR_EL1 handler

2017-06-15T08:45:05+00:00

Add a handler for reading/writing the guest's view of the ICV_CTLR_EL1
register. only EOIMode and CBPR are of interest here, as all the other
bits directly come from ICH_VTR_EL2 and are Read-Only.

Tested-by: Alexander Graf 
Acked-by: David Daney 
Acked-by: Christoffer Dall 
Reviewed-by: Eric Auger 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_RPR_EL1 handler

2017-06-15T08:45:05+00:00

Add a handler for reading the guest's view of the ICV_RPR_EL1
register, returning the highest active priority.

Tested-by: Alexander Graf 
Acked-by: David Daney 
Acked-by: Christoffer Dall 
Reviewed-by: Eric Auger 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_DIR_EL1 handler

2017-06-15T08:45:04+00:00

Add a handler for writing the guest's view of the ICC_DIR_EL1
register, performing the deactivation of an interrupt if EOImode
is set ot 1.

Tested-by: Alexander Graf 
Acked-by: David Daney 
Reviewed-by: Christoffer Dall 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add misc Group-0 handlers

2017-06-15T08:45:02+00:00

A number of Group-0 registers can be handled by the same accessors
as that of Group-1, so let's add the required system register encodings
and catch them in the dispatching function.

Tested-by: Alexander Graf 
Acked-by: David Daney 
Acked-by: Christoffer Dall 
Reviewed-by: Eric Auger 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler

2017-06-15T08:45:02+00:00

Add a handler for reading/writing the guest's view of the ICC_IGRPEN0_EL1
register, which is located in the ICH_VMCR_EL2.VENG0 field.

Tested-by: Alexander Graf 
Acked-by: David Daney 
Reviewed-by: Eric Auger 
Reviewed-by: Christoffer Dall 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm64: vgic-v3: Add ICV_BPR0_EL1 handler

2017-06-15T08:45:02+00:00

Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1
register, which is located in the ICH_VMCR_EL2.BPR0 field.

Tested-by: Alexander Graf 
Acked-by: David Daney 
Reviewed-by: Eric Auger 
Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Signed-off-by: Christoffer Dall