linux.git/virt/kvm/arm/hyp, branch v4.12

KVM: arm/arm64: vgic-v3: Fix nr_pre_bits bitfield extraction

2017-06-06T08:16:53+00:00

We used to extract PRIbits from the ICH_VT_EL2 which was the upper field
in the register word, so a mask wasn't necessary, but as we switched to
looking at PREbits, which is bits 26 through 28 with the PRIbits field
being potentially non-zero, we really need to mask off the field value,
otherwise fun things may happen.

Signed-off-by: Christoffer Dall 
Acked-by: Marc Zyngier

KVM: arm/arm64: vgic-v3: Use PREbits to infer the number of ICH_APxRn_EL2 registers

2017-05-15T09:32:04+00:00

The GICv3 documentation is extremely confusing, as it talks about
the number of priorities represented by the ICH_APxRn_EL2 registers,
while it should really talk about the number of preemption levels.

This leads to a bug where we may access undefined ICH_APxRn_EL2
registers, since PREbits is allowed to be smaller than PRIbits.
Thankfully, nobody seem to have taken this path so far...

The fix is to use ICH_VTR_EL2.PREbits instead.

Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: vgic-v3: Fix off-by-one LR access

2017-04-19T15:28:38+00:00

When iterating over the used LRs, be careful not to try to access
an unused LR, or even an unimplemented one if you're unlucky...

Reviewed-by: Christoffer Dall 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: vgic-v3: De-optimize VMCR save/restore when emulating a GICv2

2017-04-19T15:28:38+00:00

When emulating a GICv2-on-GICv3, special care must be taken to only
save/restore VMCR_EL2 when ICC_SRE_EL1.SRE is cleared. Otherwise,
all Group-0 interrupts end-up being delivered as FIQ, which is
probably not what the guest expects, as demonstrated here with
an unhappy EFI:

	FIQ Exception at 0x000000013BD21CC4

This means that we cannot perform the load/put trick when dealing
with VMCR_EL2 (because the host has SRE set), and we have to deal
with it in the world-switch.

Fortunately, this is not the most common case (modern guests should
be able to deal with GICv3 directly), and the performance is not worse
than what it was before the VMCR optimization.

Reviewed-by: Christoffer Dall 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: vgic: Get rid of MISR and EISR fields

2017-04-09T14:49:10+00:00

We don't use these fields anymore so let's nuke them completely.

Acked-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: vgic: Get rid of unnecessary save_maint_int_state

2017-04-09T14:49:09+00:00

Now when we don't look at the MISR and EISR values anymore, we can get
rid of the logic to save them in the GIC save/restore code.

Acked-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: vgic: Get rid of live_lrs

2017-04-09T14:45:31+00:00

There is no need to calculate and maintain live_lrs when we always
populate the lowest numbered LRs first on every entry and clear all LRs
on every exit.

Acked-by: Marc Zyngier 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: vgic: Defer touching GICH_VMCR to vcpu_load/put

2017-04-09T14:45:22+00:00

We don't have to save/restore the VMCR on every entry to/from the guest,
since on GICv2 we can access the control interface from EL1 and on VHE
systems with GICv3 we can access the control interface from KVM running
in EL2.

GICv3 systems without VHE becomes the rare case, which has to
save/restore the register on each round trip.

Note that userspace accesses may see out-of-date values if the VCPU is
running while accessing the VGIC state via the KVM device API, but this
is already the case and it is up to userspace to quiesce the CPUs before
reading the CPU registers from the GIC for an up-to-date view.

Reviewed-by: Marc Zyngier 
Signed-off-by: Christoffer Dall 
Signed-off-by: Christoffer Dall

KVM: arm/arm64: Move cntvoff to each timer context

2017-02-08T15:13:33+00:00

Make cntvoff per each timer context. This is helpful to abstract kvm
timer functions to work with timer context without considering timer
types (e.g. physical timer or virtual timer).

This also would pave the way for ever doing adjustments of the cntvoff
on a per-CPU basis if that should ever make sense.

Signed-off-by: Jintack Lim 
Signed-off-by: Christoffer Dall 
Signed-off-by: Marc Zyngier

KVM: arm/arm64: Abstract virtual timer context into separate structure

2017-02-08T15:13:32+00:00

Abstract virtual timer context into a separate structure and change all
callers referring to timer registers, irq state and so on. No change in
functionality.

This is about to become very handy when adding the EL1 physical timer.

Signed-off-by: Jintack Lim 
Acked-by: Christoffer Dall 
Acked-by: Marc Zyngier 
Signed-off-by: Marc Zyngier