linux.git/tools/testing/selftests/kvm/include/riscv/processor.h, branch v6.9

KVM: riscv: selftests: Add sstc timer test

2024-03-06T15:23:29+00:00

Add a KVM selftests to validate the Sstc timer functionality.
The test was ported from arm64 arch timer test.

Signed-off-by: Haibo Xu 
Reviewed-by: Andrew Jones 
Signed-off-by: Anup Patel

KVM: riscv: selftests: Change vcpu_has_ext to a common function

2024-03-06T15:23:27+00:00

Move vcpu_has_ext to the processor.c and rename it to __vcpu_has_ext
so that other test cases can use it for vCPU extension check.

Signed-off-by: Haibo Xu 
Reviewed-by: Andrew Jones 
Signed-off-by: Anup Patel

KVM: riscv: selftests: Add exception handling support

2024-03-06T15:21:41+00:00

Add the infrastructure for guest exception handling in riscv selftests.
Customized handlers can be enabled by vm_install_exception_handler(vector)
or vm_install_interrupt_handler().

The code is inspired from that of x86/arm64.

Signed-off-by: Haibo Xu 
Reviewed-by: Andrew Jones 
Signed-off-by: Anup Patel

KVM: riscv: selftests: Switch to use macro from csr.h

2024-02-26T04:44:07+00:00

Signed-off-by: Haibo Xu 
Reviewed-by: Andrew Jones 
Signed-off-by: Anup Patel

RISC-V: KVM: selftests: Add steal_time test support

2023-12-30T05:56:45+00:00

With the introduction of steal-time accounting support for
RISC-V KVM we can add RISC-V support to the steal_time test.

Reviewed-by: Anup Patel 
Reviewed-by: Atish Patra 
Signed-off-by: Andrew Jones 
Signed-off-by: Anup Patel

RISC-V: KVM: selftests: Add guest_sbi_probe_extension

2023-12-30T05:56:43+00:00

Add guest_sbi_probe_extension(), allowing guest code to probe for
SBI extensions. As guest_sbi_probe_extension() needs
SBI_ERR_NOT_SUPPORTED, take the opportunity to bring in all SBI
error codes. We don't bring in all current extension IDs or base
extension function IDs though, even though we need one of each,
because we'd prefer to bring those in as necessary.

Reviewed-by: Anup Patel 
Reviewed-by: Atish Patra 
Signed-off-by: Andrew Jones 
Signed-off-by: Anup Patel

KVM: riscv: selftests: Add RISCV_SBI_EXT_REG

2023-12-29T07:01:47+00:00

While adding RISCV_SBI_EXT_REG(), acknowledge that some registers
have subtypes and extend __kvm_reg_id() to take a subtype field.
Then, update all macros to set the new field appropriately. The
general CSR macro gets renamed to include "GENERAL", but the other
macros, like the new RISCV_SBI_EXT_REG, just use the SINGLE subtype.

Signed-off-by: Andrew Jones 
Reviewed-by: Anup Patel 
Signed-off-by: Anup Patel

KVM: riscv: selftests: Add get-reg-list test

2023-08-09T06:45:27+00:00

get-reg-list test is used to check for KVM registers regressions
during VM migration which happens when destination host kernel
missing registers that the source host kernel has. The blessed
list registers was created by running on v6.5-rc3

Signed-off-by: Haibo Xu 
Reviewed-by: Andrew Jones 
Signed-off-by: Anup Patel

KVM: selftests: Consolidate KVM_{G,S}ET_ONE_REG helpers

2022-06-11T15:47:10+00:00

Rework vcpu_{g,s}et_reg() to provide the APIs that tests actually want to
use, and drop the three "one-off" implementations that cropped up due to
the poor API.

Ignore the handful of direct KVM_{G,S}ET_ONE_REG calls that don't fit the
APIs for one reason or another.

No functional change intended.

Signed-off-by: Sean Christopherson 
Signed-off-by: Paolo Bonzini

KVM: selftests: riscv: Improve unexpected guest trap handling

2022-05-20T03:38:56+00:00

Currently, we simply hang using "while (1) ;" upon any unexpected
guest traps because the default guest trap handler is guest_hang().

The above approach is not useful to anyone because KVM selftests
users will only see a hung application upon any unexpected guest
trap.

This patch improves unexpected guest trap handling for KVM RISC-V
selftests by doing the following:
1) Return to host user-space
2) Dump VCPU registers
3) Die using TEST_ASSERT(0, ...)

Signed-off-by: Anup Patel 
Tested-by: Mayuresh Chitale 
Signed-off-by: Anup Patel