linux.git/include/uapi/drm/drm_fourcc.h, branch v5.8

drm: Generalized NV Block Linear DRM format mod

2020-05-22T00:53:33+00:00

Builds upon the existing NVIDIA 16Bx2 block linear
format modifiers by adding more "fields" to the
existing parameterized
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK format modifier
macro that allow fully defining a unique-across-
all-NVIDIA-hardware bit layout using a minimal
set of fields and values.  The new modifier macro
DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D is
effectively backwards compatible with the existing
macro, introducing a superset of the previously
definable format modifiers.

Backwards compatibility has two quirks.  First,
the zero value for the "kind" field, which is
implied by the DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK
macro, must be special cased in drivers and
assumed to map to the pre-Turing generic kind of
0xfe, since a kind of "zero" is reserved for
linear buffer layouts on all GPUs.

Second, it is assumed backwards compatibility
is only needed when running on Tegra GPUs, and
specifically Tegra GPUs prior to Xavier.  This
is based on two assertions:

-Tegra GPUs prior to Xavier used a slightly
 different raw bit layout than desktop GPUs,
 making it impossible to directly share block
 linear buffers between the two.

-Support for the existing block linear modifiers
 was incomplete, making them useful only for
 exporting buffers created by nouveau and
 importing them to Tegra DRM as framebuffers for
 scan out.  There was no support for adding
 framebuffers using format modifiers in nouveau,
 nor importing dma-buf/PRIME GEM objects into
 nouveau userspace drivers with modifiers in Mesa.

Hence it is assumed the prior modifiers were not
intended for use on desktop GPUs, and as a
corollary, were not intended to support sharing
block linear buffers across two different NVIDIA
GPUs.

v2:
  - Added canonicalize helper function

v3:
  - Added additional bit to compression field to
    support Tesla (NV5x,G8x,G9x,GT1xx,GT2xx) class
    chips.

Signed-off-by: James Jones 
Signed-off-by: Ben Skeggs

uapi/drm/drm_fourcc.h: Note on platform specificity for format modifiers

2020-05-08T10:12:58+00:00

Make an additional note on DRM format modifiers for x and y tiling. These
format modifiers are defined for BDW+ platforms and therefore definition
is not valid for older gens. This is due to address swizzling for tiled
surfaces is no longer used. For newer platforms main memory controller has
a more effective address swizzling algorithm.

v2: Rephrase comment (Daniel)

Signed-off-by: Mika Kahola 
Signed-off-by: Daniel Vetter 
Link: https://patchwork.freedesktop.org/patch/msgid/20200506120827.12250-1-mika.kahola@intel.com

drm/framebuffer: Format modifier for Intel Gen-12 media compression

2020-01-07T11:15:48+00:00

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

v2: Update code comment describing the color plane order for YUV
    semiplanar formats.

Cc: Nanley G Chery 
Cc: Matt Roper 
Cc: Ville Syrjälä 
Cc: Mika Kahola 
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan 
Signed-off-by: Lucas De Marchi 
Signed-off-by: Imre Deak 
Reviewed-by: Mika Kahola 
Link: https://patchwork.freedesktop.org/patch/msgid/20191231233756.18753-6-imre.deak@intel.com

drm/framebuffer: Format modifier for Intel Gen-12 render compression

2019-12-23T11:50:56+00:00

Gen-12 has a new compression format, add a new modifier to indicate that.

Cc: Ville Syrjälä 
Cc: Matt Roper 
Cc: Nanley G Chery 
Cc: Jason Ekstrand 
Cc: Mika Kahola 
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan 
Signed-off-by: Lucas De Marchi 
Signed-off-by: Imre Deak 
Reviewed-by: Mika Kahola 
Link: https://patchwork.freedesktop.org/patch/msgid/20191221120543.22816-6-imre.deak@intel.com

drm/fourcc: Fix undefined left shift in DRM_FORMAT_BIG_ENDIAN macros

2019-10-18T18:19:24+00:00

1<<31 is undefined because it's a signed int and C is terrible.

Reviewed-by: Eric Engestrom 
Signed-off-by: Adam Jackson 
Signed-off-by: Ville Syrjälä 
Link: https://patchwork.freedesktop.org/patch/msgid/20191018175041.613780-1-ajax@redhat.com

drm/fourcc: Add Arm 16x16 block modifier

2019-10-04T14:22:41+00:00

Add the DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED modifier to
denote the 16x16 block u-interleaved format used in Arm Utgard and
Midgard GPUs.

Changes from v1:-
1. Reserved the upper four bits (out of the 56 bits assigned to each vendor)
to denote the category of Arm specific modifiers. Currently, we have two
categories ie AFBC and MISC.

Changes from v2:-
1. Preserved Ray's authorship
2. Cleanups/changes suggested by Brian
3. Added r-bs of Brian and Qiang

Signed-off-by: Raymond Smith 
Reviewed-by: Brian Starkey 
Reviewed-by: Qiang Yu 
Signed-off-by: Ayan kumar halder 
Link: https://patchwork.freedesktop.org/patch/msgid/20191004141222.22337-1-ayan.halder@arm.com

drm/fourcc: Fix conflicting Y41x definitions

2019-03-21T08:49:04+00:00

There has unfortunately been a conflict with the following 3 commits:

commit e9961ab95af81b8d29054361cd5f0c575102cf87
Author: Ayan Kumar Halder 
Date:   Fri Nov 9 17:21:12 2018 +0000
    drm: Added a new format DRM_FORMAT_XVYU2101010

commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3
Author: Brian Starkey 
Date:   Fri Oct 5 10:27:00 2018 +0100

    drm/fourcc: Add AFBC yuv fourccs for Mali

and

commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b
Author: Swati Sharma 
Date:   Mon Mar 4 17:26:33 2019 +0530

    drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

Unfortunately gcc didn't warn about the redefinitions, because the
double defines were the set to same value, and gcc apparently no longer
warns about that.

Fix this by using new XYVU for i915, without alpha, and making the
Y41x definitions match msdn, with alpha.

Fortunately we caught it early, and the conflict hasn't even landed in
drm-next yet.

Signed-off-by: Maarten Lankhorst 
Cc: Brian Starkey 
Cc: Swati Sharma 
Cc: Ayan Kumar Halder 
Cc: malidp@foss.arm.com
Cc: Daniel Vetter 
Cc: Maxime Ripard 
Cc: Sean Paul 
Cc: Dave Airlie 
Cc: Liviu Dudau 
Link: https://patchwork.freedesktop.org/patch/msgid/20190319121702.6814-1-maarten.lankhorst@linux.intel.com
Acked-by: Jani Nikula  #irc
Acked-by: Sean Paul 
Reviewed-by: Ayan Kumar halder

Merge tag 'topic/hdr-formats-2019-03-13' of git://anongit.freedesktop.org/drm/drm-misc into drm-misc-next

2019-03-13T18:08:05+00:00

Add support for floating point half-width formats.

Signed-off-by: Sean Paul 

From: Maarten Lankhorst 
Link: https://patchwork.freedesktop.org/patch/msgid/00b96cd5-91c7-5677-9620-b138c7a92303@linux.intel.com

drm/fourcc: Add 64 bpp half float formats

2019-03-13T10:10:31+00:00

Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
formatted in IEEE-754 half-precision float (binary16) 1:5:10
MSb-sign:exponent:fraction form.

This patch attempts to address the feedback provided when 2 of these
formats were previosly proposed:
  https://patchwork.kernel.org/patch/10072545/

v2:
- Fixed cpp (Ville)
- Added detail pixel formatting (Ville)
- Ordered formats in header (Ville)

v5:
- .depth should be 0 for new formats (Maarten)

Cc: Tina Zhang 
Cc: Uma Shankar 
Cc: Shashank Sharma 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser 
Reviewed-by: Ville Syrjälä 
Reviewed-by: Maarten Lankhorst 
Reviewed-by: Adam Jackson 
Signed-off-by: Maarten Lankhorst 
Link: https://patchwork.freedesktop.org/patch/msgid/1552437513-22648-2-git-send-email-kevin.strasser@intel.com

drm: Added a new format DRM_FORMAT_XVYU2101010

2019-03-12T18:25:05+00:00

This new format is supported by DP550 and DP650

Changes since v3 (series):
- Added the ack
- Rebased on the latest drm-misc-next

Signed-off-by: Ayan Kumar halder 
Reviewed-by: Liviu Dudau 
Acked-by: Alyssa Rosenzweig 
Link: https://patchwork.freedesktop.org/patch/291758/?series=57895&rev=1