linux.git/include/linux/mtd, branch v6.14

mtd: spinand: Add support for read DTR operations

2025-01-15T18:24:03+00:00

Advanced SPI-NAND chips are capable of reading data much faster by
leveraging DTR support. This support extends to dual and quad
configurations.

Create macros defining all possible read from cache DTR variants:
- SPINAND_PAGE_READ_FROM_CACHE_DTR_OP
- SPINAND_PAGE_READ_FROM_CACHE_X2_DTR_OP
- SPINAND_PAGE_READ_FROM_CACHE_X4_DTR_OP
- SPINAND_PAGE_READ_FROM_CACHE_DUALIO_DTR_OP
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_DTR_OP

Signed-off-by: Miquel Raynal

mtd: spinand: Add an optional frequency to read from cache macros

2025-01-15T18:23:47+00:00

While the SPINAND_PAGE_READ_FROM_CACHE_FAST_OP macro is supposed to be
able to run at the flash highest supported frequency, it is not the case
of the regular read from cache, which may be limited in terms of maximum
frequency. Add an optional argument to this macro, which will be used to
set the maximum frequency, if any.

Signed-off-by: Miquel Raynal

mtd: spinand: Create distinct fast and slow read from cache variants

2025-01-15T18:23:28+00:00

So far, the SPINAND_PAGE_READ_FROM_CACHE_OP macro was taking a first
argument, "fast", which was inducing the possibility to support higher
bus frequencies than with the normal (slower) read from cache
alternative. In practice, without frequency change on the bus, this was
likely without effect, besides perhaps allowing another variant of the
same command, that could run at the default highest speed. If we want to
support this fully, we need to add a frequency parameter to the slowest
command. But before we do that, let's drop the "fast" boolean from the
macro and duplicate it, this will further help supporting having
different frequencies allowed for each variant.

The change is also of course propagated to all users. It has the nice
effect to have all macros aligned on the same pattern.

Reviewed-by: Tudor Ambarus 
Signed-off-by: Miquel Raynal

mtd: rawnand: qcom: Fix build issue on x86 architecture

2025-01-08T18:26:39+00:00

Fix a buffer overflow issue in qcom_clear_bam_transaction by using
struct_group to group related fields and avoid FORTIFY_SOURCE warnings.

On x86 architecture, the following error occurs due to warnings being
treated as errors:

In function ‘fortify_memset_chk’,
    inlined from ‘qcom_clear_bam_transaction’ at
drivers/mtd/nand/qpic_common.c:88:2:
./include/linux/fortify-string.h:480:25: error: call to ‘__write_overflow_field’
declared with attribute warning: detected write beyond size of field
(1st parameter); maybe use struct_group()? [-Werror=attribute-warning]
  480 |                         __write_overflow_field(p_size_field, size);
      |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  LD [M]  drivers/mtd/nand/nandcore.o
  CC [M]  drivers/w1/masters/mxc_w1.o
cc1: all warnings being treated as errors

This patch addresses the issue by grouping the related fields in
struct bam_transaction using struct_group and updating the memset call
accordingly.

Fixes: 8c52932da5e6 ("mtd: rawnand: qcom: cleanup qcom_nandc driver")
Signed-off-by: Md Sadre Alam 
Signed-off-by: Miquel Raynal

Merge tag 'mtd/qcom-reorg-for-spi-6.14' into nand/next

2024-12-24T15:44:01+00:00

Topic branch with preparation changes from Qcom in order to apply on top
the spi bits adding the Qcom SPI-NAND controller driver re-using a lot
of code that has been shared.

With this goal in mind, the raw NAND controller driver has been cleaned
up and reorganized, and only the relevant structures/helpers which have
nothing raw NAND specific should now be exported.

mtd: rawnand: qcom: use FIELD_PREP and GENMASK

2024-12-24T15:22:02+00:00

Use the bitfield macro FIELD_PREP, and GENMASK to
do the shift and mask in one go. This makes the code
more readable.

Reviewed-by: Konrad Dybcio 
Signed-off-by: Md Sadre Alam 
Signed-off-by: Miquel Raynal

mtd: nand: Add qpic_common API file

2024-12-24T15:22:02+00:00

Add qpic_common.c file which hold all the common
qpic APIs which will be used by both qpic raw nand
driver and qpic spi nand driver.

Signed-off-by: Md Sadre Alam 
Signed-off-by: Miquel Raynal

mtd: spinand: Add support for SkyHigh S35ML-3 family

2024-12-05T10:14:21+00:00

SkyHigh S35ML01G300, S35ML01G301, S35ML02G300, and S35ML04G300 are 1Gb,
2Gb, and 4Gb SLC SPI NAND flash family. This family of devices has
on-die ECC which parity bits are stored to hidden area. In this family
the on-die ECC cannot be disabled so raw access needs to be prevented.

Link: https://www.skyhighmemory.com/download/SPI_S35ML01_04G3_002_19205.pdf?v=P
Co-developed-by: KR Kim 
Signed-off-by: KR Kim 
Signed-off-by: Takahiro Kuwano 
Signed-off-by: Miquel Raynal

mtd: spinand: Introduce a way to avoid raw access

2024-12-05T10:14:21+00:00

SkyHigh spinand device has ECC enable bit in configuration register but
it must be always enabled. If ECC is disabled, read and write ops
results in undetermined state. For such devices, a way to avoid raw
access is needed.

Introduce SPINAND_NO_RAW_ACCESS flag to advertise the device does not
support raw access. In such devices, the on-die ECC engine ops returns
error to I/O request in raw mode.

Checking and marking BBM need to be cared as special case, by adding
fallback mechanism that tries read/write OOB with ECC enabled.

Signed-off-by: Takahiro Kuwano 
Signed-off-by: Miquel Raynal

Merge tag 'mtd/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

2024-11-23T01:06:59+00:00

Pull MTD updates from Miquel Raynal:
 "MTD device changes:
   - switch platform_driver back to remove()
   - misc fixes

  SPI-NAND changes:
   - a load of fixes to Winbond manufacturer driver
   - structure constification

  Raw NAND changes:
   - improve the power management of the GPMI driver
   - Davinci driver clean-ups
   - fix leak in the Atmel driver
   - fix some typos in the core

  SPI NOR changes:
   - Introduce byte swap support for 8D-8D-8D mode and a user for it:
     macronix.

     SPI NOR flashes may swap the bytes on a 16-bit boundary when
     configured in Octal DTR mode. For such cases the byte order is
     propagated through SPI MEM to the SPI controllers so that the
     controllers swap the bytes back at runtime. This avoids breaking
     the boot sequence because of the endianness problems that appear
     when the bootloaders use 1-1-1 and the kernel uses 8D-8D-8D with
     byte swap support. Along with the SPI MEM byte swap support we
     queue a patch for the SPI MXIC controller that swaps the bytes back
     at runtime"

* tag 'mtd/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (25 commits)
  mtd: spi-nor: core: replace dummy buswidth from addr to data
  mtd: spi-nor: winbond: add "w/ and w/o SFDP" comment
  mtd: spi-nor: spansion: Use nor->addr_nbytes in octal DTR mode in RD_ANY_REG_OP
  mtd: Switch back to struct platform_driver::remove()
  mtd: cfi_cmdset_0002: remove redundant assignment to variable ret
  mtd: spinand: Constify struct nand_ecc_engine_ops
  MAINTAINERS: add mailing list for GPMI NAND driver
  mtd: spinand: winbond: Sort the devices
  mtd: spinand: winbond: Ignore the last ID characters
  mtd: spinand: winbond: Fix 512GW, 01GW, 01JW and 02JW ECC information
  mtd: spinand: winbond: Fix 512GW and 02JW OOB layout
  mtd: nand: raw: gpmi: improve power management handling
  mtd: nand: raw: gpmi: switch to SYSTEM_SLEEP_PM_OPS
  mtd: rawnand: davinci: use generic device property helpers
  mtd: rawnand: davinci: break the line correctly
  mtd: rawnand: davinci: order headers alphabetically
  mtd: rawnand: atmel: Fix possible memory leak
  mtd: rawnand: Correct multiple typos in comments
  mtd: hyperbus: rpc-if: Add missing MODULE_DEVICE_TABLE
  mtd: spi-nor: add support for Macronix Octal flash
  ...