linux.git/include/linux/mmc, branch v3.19

mmc: sdhci: Disable re-tuning for HS400

2015-01-12T09:14:56+00:00

Re-tuning for HS400 mode must be done in HS200
mode. Currently there is no support for that.
That needs to be reflected in the code.
Specifically, if tuning is executed in HS400 mode
then return an error, and do not start the
tuning timer if HS200 tuning is being done prior
to switching to HS400.

Note that periodic re-tuning is not expected
to be needed for HS400 but re-tuning is still
needed after the host controller has lost power.
In the case of suspend/resume that is not necessary
because the card is fully re-initialised. That
just leaves runtime suspend/resume with no support
for HS400 re-tuning.

Signed-off-by: Adrian Hunter 
Signed-off-by: Ulf Hansson

mmc: core: Let mmc_send_tuning() to take struct mmc_host* as parameter

2014-12-08T08:11:04+00:00

To be able to use mmc_send_tuning() prior the struct mmc_card has been
allocated, let's convert it to take the struct mmc_host* as parameter
instead.

Suggested-by: Stephen Boyd 
Signed-off-by: Ulf Hansson 
Acked-by: Dong Aisheng 
Reviewed-by: Stephen Boyd

mmc: core: add core-level function for sending tuning commands

2014-11-26T13:36:51+00:00

According to the SD card spec, Add a manual tuning command function
for SDR104/HS200.
Sending command 19 or command 21 to read data and compare with the
tunning block pattern.

This patch will help to decrease some platform private codes in SDHCI
platform_execute_tuning() callbacks.

Signed-off-by: Minda Chen 
Signed-off-by: Barry Song 
Signed-off-by: Ulf Hansson

mmc: dw_mmc: add support for the other bit of sdio interrupt

2014-11-26T13:31:00+00:00

The bit of sdio interrupt is 16 in designware implementation,
but it is 24 on Rockchip SoCs.This patch add sdio_id0 for the
number of slot0 in the SDIO interrupt registers.

Signed-off-by: Addy Ke 
Reviewed-by: Doug Anderson 
Acked-by: Jaehoon Chung 
Signed-off-by: Ulf Hansson

mmc: sdhci: Add HS400 support to SDHCI driver

2014-11-26T13:30:52+00:00

MMC core already has support for HS400.  Add HS400
support to SDHCI driver.  The SDHC Standard specification
does not define HS400 so consequently HS400 support is
non-standard.  However HS400 is not selected without
the host controller setting the corresponding capability
flags so host controllers not yet supporting HS400
will not be affected.  To support that, a quirk
SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 is introduced to
enable the use of capabilities register reserved bit-63
to indicate HS400 support.

Because HS400 is non-standard for SDHCI, it is possible
that different vendors will do things in different ways.
However HS200 support faced the same issue but currently
there is only one solution.  As such, no attempt has
been made to provide for alternate HS400 solutions except
for SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400.

Signed-off-by: Adrian Hunter 
Signed-off-by: Ulf Hansson

mmc: sdhci: Clear also HS400 1.2V capability if 1.2V is not supported

2014-11-26T13:30:51+00:00

1.2V HS200 mode capability is cleared if there is not a voltage
regulator that supports 1.2V.  Do the same for 1.2V HS400 mode.

Signed-off-by: Adrian Hunter 
Signed-off-by: Ulf Hansson

mmc: dw_mmc: Add IDMAC 64-bit address mode support

2014-11-26T13:30:50+00:00

Synopsys DW_MMC IP core supports Internal DMA Controller with 64-bit address mode from IP version 2.70a onwards.
Updated the driver to support IDMAC 64-bit addressing mode.

Signed-off-by: Prabu Thangamuthu 
Reviewed-by: Alim Akhtar 
Acked-by: Jaehoon Chung 
Signed-off-by: Ulf Hansson

mmc: sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

2014-11-26T13:30:28+00:00

SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms

Signed-off-by: Vincent Wan 
Signed-off-by: Wan Zongshun 
Signed-off-by: Arindam Nath 
Tested-by: Vikram B 
Tested-by: Raghavendra Swamy 
Signed-off-by: Ulf Hansson

mmc: sdhci: Add 64-bit ADMA support

2014-11-10T11:40:53+00:00

Add 64-bit ADMA support including:
	- add 64-bit ADMA descriptor
	- add SDHCI_USE_64_BIT_DMA flag
	- set upper 32-bits of DMA addresses
	- ability to select 64-bit ADMA
	- ability to use 64-bit ADMA sizes and alignment
	- display "ADMA 64-bit" when host is added

It is assumed that a 64-bit capable device has set a 64-bit DMA mask
and *must* do 64-bit DMA.  A driver has the opportunity to change
that during the first call to ->enable_dma().  Similarly
SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
implement.

Signed-off-by: Adrian Hunter 
Signed-off-by: Ulf Hansson

mmc: sdhci: Parameterize ADMA sizes and alignment

2014-11-10T11:40:51+00:00

In preparation for 64-bit ADMA, parameterize ADMA sizes
and alignment.  64-bit ADMA has a larger descriptor
because it contains a 64-bit address instead of a 32-bit
address.  Also data must be 8-byte aligned instead
of 4-byte aligned.  Consequently, sdhci_host members
are added for descriptor, table, and buffer sizes
and alignment.

Signed-off-by: Adrian Hunter 
Signed-off-by: Ulf Hansson