linux.git/include/linux/mlx5, branch v6.10

net/mlx5: IFC updates for changing max EQs

2024-06-28T11:58:10+00:00

Expose new capability to support changing the number of EQs available
to other functions.

Fixes: 93197c7c509d ("mlx5/core: Support max_io_eqs for a function")
Signed-off-by: Daniel Jurgens 
Reviewed-by: Parav Pandit 
Reviewed-by: William Tu 
Signed-off-by: Tariq Toukan 
Signed-off-by: David S. Miller

net/mlx5: Fix MTMP register capability offset in MCAM register

2024-05-24T12:27:07+00:00

The MTMP register (0x900a) capability offset is off-by-one, move it to
the right place.

Fixes: 1f507e80c700 ("net/mlx5: Expose NIC temperature via hardware monitoring kernel API")
Signed-off-by: Gal Pressman 
Reviewed-by: Cosmin Ratiu 
Signed-off-by: Tariq Toukan 
Reviewed-by: Simon Horman 
Signed-off-by: David S. Miller

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

2024-05-14T17:53:19+00:00

Merge in late fixes to prepare for the 6.10 net-next PR.

Signed-off-by: Jakub Kicinski

net/mlx5: Remove unused msix related exported APIs

2024-05-13T23:35:47+00:00

MSIX irq allocation and free APIs are no longer
in use. Hence, remove the dead code.

Signed-off-by: Parav Pandit 
Reviewed-by: Dragos Tatulea 
Signed-off-by: Tariq Toukan 
Reviewed-by: Simon Horman 
Reviewed-by: Kalesh AP 
Link: https://lore.kernel.org/r/20240512124306.740898-4-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski

net/mlx5: Enable 8 ports LAG

2024-05-13T23:35:47+00:00

This patch adds to mlx5 drivers support for 8 ports HCAs.
Starting with ConnectX-8 HCAs with 8 ports are possible.

As most driver parts aren't affected by such configuration most driver
code is unchanged.

Specially the only affected areas are:
- Lag
- Multiport E-Switch
- Single FDB E-Switch

All of the above are already factored in generic way, and LAG and VF LAG
are tested, so all that left is to change a #define and remove checks
which are no longer needed.
However, Multiport E-Switch is not tested yet, so it is left untouched.

This patch will allow to create hardware LAG/VF LAG when all 8 ports are
added to the same bond device.

for example, In order to activate the hardware lag a user can execute
the following:

ip link add bond0 type bond
ip link set bond0 type bond miimon 100 mode 2
ip link set eth2 master bond0
ip link set eth3 master bond0
ip link set eth4 master bond0
ip link set eth5 master bond0
ip link set eth6 master bond0
ip link set eth7 master bond0
ip link set eth8 master bond0
ip link set eth9 master bond0

Where eth2, eth3, eth4, eth5, eth6, eth7, eth8 and eth9 are the PFs of
the same HCA.

Signed-off-by: Shay Drory 
Reviewed-by: Mark Bloch 
Signed-off-by: Tariq Toukan 
Reviewed-by: Simon Horman 
Link: https://lore.kernel.org/r/20240512124306.740898-2-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski

net/mlx5: Add a timeout to acquire the command queue semaphore

2024-05-11T02:38:33+00:00

Prevent forced completion handling on an entry that has not yet been
assigned an index, causing an out of bounds access on idx = -22.
Instead of waiting indefinitely for the sem, blocking flow now waits for
index to be allocated or a sem acquisition timeout before beginning the
timer for FW completion.

Kernel log example:
mlx5_core 0000:06:00.0: wait_func_handle_exec_timeout:1128:(pid 185911): cmd[-22]: CREATE_UCTX(0xa04) No done completion

Fixes: 8e715cd613a1 ("net/mlx5: Set command entry semaphore up once got index free")
Signed-off-by: Akiva Goldberger 
Reviewed-by: Moshe Shemesh 
Signed-off-by: Tariq Toukan 
Link: https://lore.kernel.org/r/20240509112951.590184-5-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski

net/mlx5e: Support updating coalescing configuration without resetting channels

2024-04-22T21:22:16+00:00

When CQE mode or DIM state is changed, gracefully reconfigure channels to
handle new configuration. Previously, would create new channels that would
reflect the changes rather than update the original channels.

Co-developed-by: Nabil S. Alramli 
Signed-off-by: Nabil S. Alramli 
Co-developed-by: Joe Damato 
Signed-off-by: Joe Damato 
Signed-off-by: Rahul Rameshbabu 
Signed-off-by: Tariq Toukan 
Link: https://lore.kernel.org/r/20240419080445.417574-5-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski

net/mlx5e: Use DIM constants for CQ period mode parameter

2024-04-22T21:22:16+00:00

Use core DIM CQ period mode enum values for the CQ parameter for the period
mode. Translate the value to the specific mlx5 device constant for the
selected period mode when creating a CQ. Avoid needing to translate mlx5
device constants to DIM constants for core DIM functionality.

Co-developed-by: Nabil S. Alramli 
Signed-off-by: Nabil S. Alramli 
Co-developed-by: Joe Damato 
Signed-off-by: Joe Damato 
Signed-off-by: Rahul Rameshbabu 
Signed-off-by: Tariq Toukan 
Link: https://lore.kernel.org/r/20240419080445.417574-3-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski

net/mlx5e: Support FEC settings for 100G/lane modes

2024-04-06T04:54:40+00:00

This consists of:
1. Expose the 100G/lane capability bit in the PCAM reg.
2. Expose the per link mode FEC capability masks in the PPLM reg.
3. Set the overrides according to ethtool parameters.
FEC for new modes is set if and only if the PCAM 100G/lane capability is
advertised and the capability mask for a given link mode reports that it
can accept the requested FEC mode.

Signed-off-by: Cosmin Ratiu 
Reviewed-by: Gal Pressman 
Signed-off-by: Tariq Toukan 
Link: https://lore.kernel.org/r/20240404173357.123307-3-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski

net/mlx5: Skip pages EQ creation for non-page supplier function

2024-04-04T02:47:59+00:00

Page events are not issued by device on the function if
page_request_disable is set, so no need to create pages EQ.

Signed-off-by: Jianbo Liu 
Reviewed-by: Parav Pandit 
Reviewed-by: Moshe Shemesh 
Signed-off-by: Tariq Toukan 
Link: https://lore.kernel.org/r/20240402133043.56322-11-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski