linux.git/include/linux/coresight.h, branch v7.1-rc2

coresight: Fix memory leak in coresight_alloc_device_name()

2026-02-25T11:14:44+00:00

The memory leak detector reports:

  echo clear > /sys/kernel/debug/kmemleak
  modprobe coresight_funnel
  rmmod coresight_funnel

  # Scan memory leak and report it
  echo scan > /sys/kernel/debug/kmemleak
  cat /sys/kernel/debug/kmemleak
  unreferenced object 0xffff0008020c7200 (size 64):
    comm "modprobe", pid 410, jiffies 4295333721
    hex dump (first 32 bytes):
      d8 da fe 7e 09 00 ff ff e8 2e ff 7e 09 00 ff ff  ...~.......~....
      b0 6c ff 7e 09 00 ff ff 30 83 00 7f 09 00 ff ff  .l.~....0.......
    backtrace (crc 4116a690):
      kmemleak_alloc+0xd8/0xf8
      __kmalloc_node_track_caller_noprof+0x2c8/0x6f0
      krealloc_node_align_noprof+0x13c/0x2c8
      coresight_alloc_device_name+0xe4/0x158 [coresight]
      0xffffd327ecef8394
      0xffffd327ecef85ec
      amba_probe+0x118/0x1c8
      really_probe+0xc8/0x3f0
      __driver_probe_device+0x88/0x190
      driver_probe_device+0x44/0x120
      __driver_attach+0x100/0x238
      bus_for_each_dev+0x84/0xf0
      driver_attach+0x2c/0x40
      bus_add_driver+0x128/0x258
      driver_register+0x64/0x138
      __amba_driver_register+0x2c/0x48

The memory leak is caused by not freeing the device list that maintains
device indices.

This device list preserves stable device indices across unbind and
rebind device operations, so it does not share the same lifetime as a
device instances and must only be freed when the module is unloaded.

Some modules do not implement a module exit callback because they are
registered using module_platform_driver().  As a result, the device
list cannot be released during module exit for those modules.

Fix this by moving the device list into the core layer.  As a general
solution, instead of maintaining a static list in each driver, drivers
now allocate device lists via coresight_allocate_device_list() and
device indices via coresight_allocate_device_idx().

The list is released only when the core module is unloaded by calling
coresight_release_device_list(), avoiding the leak.

Fixes: 0f5f9b6ba9e1 ("coresight: Use platform agnostic names")
Reviewed-by: James Clark 
Signed-off-by: Leo Yan 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20260209-arm_coresight_refactor_dev_register-v4-1-62d6042f76f7@arm.com

coresight: Change device mode to atomic type

2025-11-11T21:47:57+00:00

The device mode is defined as local type. This type cannot promise
SMP-safe access.

Change to atomic type and impose relax ordering, which ensures the
SMP-safe synchronisation and the ordering between the mode setting and
relevant operations.

Fixes: 22fd532eaa0c ("coresight: etm3x: adding operation mode for etm_enable()")
Reviewed-by: Mike Leach 
Tested-by: James Clark 
Signed-off-by: Leo Yan 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-1-f55553b6c8b3@arm.com

coresight: change the sink_ops to accept coresight_path

2025-11-10T10:07:42+00:00

Update the sink_enable functions to accept coresight_path instead of
a generic void *data, as coresight_path encapsulates all the necessary
data required by devices along the path.

Tested-by: Carl Worth 
Reviewed-by: Carl Worth 
Reviewed-by: Leo Yan 
Signed-off-by: Jie Gan 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20250925-fix_helper_data-v2-3-edd8a07c1646@oss.qualcomm.com

coresight: change helper_ops to accept coresight_path

2025-11-10T10:07:41+00:00

Update the helper_enable and helper_disable functions to accept
coresight_path instead of a generic void *data, as coresight_path
encapsulates all the necessary data required by devices along the path.

Tested-by: Carl Worth 
Reviewed-by: Carl Worth 
Reviewed-by: Leo Yan 
Signed-off-by: Jie Gan 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20250925-fix_helper_data-v2-2-edd8a07c1646@oss.qualcomm.com

coresight: tmc: add the handle of the event to the path

2025-11-10T10:07:35+00:00

The handle is essential for retrieving the AUX_EVENT of each CPU and is
required in perf mode. It has been added to the coresight_path so that
dependent devices can access it from the path when needed.

The existing bug can be reproduced with:
perf record -e cs_etm//k -C 0-9 dd if=/dev/zero of=/dev/null

Showing an oops as follows:
Unable to handle kernel paging request at virtual address 000f6e84934ed19e

Call trace:
 tmc_etr_get_buffer+0x30/0x80 [coresight_tmc] (P)
 catu_enable_hw+0xbc/0x3d0 [coresight_catu]
 catu_enable+0x70/0xe0 [coresight_catu]
 coresight_enable_path+0xb0/0x258 [coresight]

Fixes: 080ee83cc361 ("Coresight: Change functions to accept the coresight_path")
Signed-off-by: Carl Worth 
Reviewed-by: Leo Yan 
Co-developed-by: Jie Gan 
Signed-off-by: Jie Gan 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20250925-fix_helper_data-v2-1-edd8a07c1646@oss.qualcomm.com

coresight: Consolidate clock enabling

2025-09-23T13:14:12+00:00

CoreSight drivers enable pclk and atclk conditionally. For example,
pclk is only enabled in the static probe, while atclk is an optional
clock that it is enabled for both dynamic and static probes, if it is
present. In the current CoreSight drivers, these two clocks are
initialized separately.  This causes complex and duplicate codes.

CoreSight drivers are refined so that clocks are initialized in one go.
For this purpose, this commit renames coresight_get_enable_apb_pclk() to
coresight_get_enable_clocks() and encapsulates clock initialization
logic:

 - If a clock is initialized successfully, its clock pointer is assigned
   to the double pointer passed as an argument.
 - For ACPI devices, clocks are controlled by firmware, directly bail
   out.
 - Skip enabling pclk for an AMBA device.
 - If atclk is not found, the corresponding double pointer is set to
   NULL. The function returns Success (0) to guide callers can proceed
   with no error.
 - Otherwise, an error number is returned for failures.

The function became complex, move it from the header to the CoreSight
core layer and the symbol is exported. Added comments for recording
details.

Suggested-by: Suzuki K Poulose 
Reviewed-by: Anshuman Khandual 
Reviewed-by: Yeoreum Yun 
Tested-by: James Clark 
Signed-off-by: Leo Yan 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20250731-arm_cs_fix_clock_v4-v6-7-1dfe10bb3f6f@arm.com

coresight: Avoid enable programming clock duplicately

2025-09-23T13:14:12+00:00

The programming clock is enabled by AMBA bus driver before a dynamic
probe. As a result, a CoreSight driver may redundantly enable the same
clock.

To avoid this, add a check for device type and skip enabling the
programming clock for AMBA devices. The returned NULL pointer will be
tolerated by the drivers.

Fixes: 73d779a03a76 ("coresight: etm4x: Change etm4_platform_driver driver for MMIO devices")
Reviewed-by: Anshuman Khandual 
Reviewed-by: Yeoreum Yun 
Tested-by: James Clark 
Signed-off-by: Leo Yan 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20250731-arm_cs_fix_clock_v4-v6-6-1dfe10bb3f6f@arm.com

coresight: Appropriately disable programming clocks

2025-09-23T13:14:12+00:00

Some CoreSight components have programming clocks (pclk) and are enabled
using clk_get() and clk_prepare_enable().  However, in many cases, these
clocks are not disabled when modules exit and only released by clk_put().

To fix the issue, this commit refactors programming clock by replacing
clk_get() and clk_prepare_enable() with devm_clk_get_optional_enabled()
for enabling APB clock. If the "apb_pclk" clock is not found, a NULL
pointer is returned, and the function proceeds to attempt enabling the
"apb" clock.

Since ACPI platforms rely on firmware to manage clocks, returning a NULL
pointer in this case leaves clock management to the firmware rather than
the driver. This effectively avoids a clock imbalance issue during
module removal - where the clock could be disabled twice: once during
the ACPI runtime suspend and again during the devm resource release.

Callers are updated to reuse the returned error value.

With the change, programming clocks are managed as resources in driver
model layer, allowing clock cleanup to be handled automatically.  As a
result, manual cleanup operations are no longer needed and are removed
from the Coresight drivers.

Fixes: 73d779a03a76 ("coresight: etm4x: Change etm4_platform_driver driver for MMIO devices")
Reviewed-by: Yeoreum Yun 
Tested-by: James Clark 
Signed-off-by: Leo Yan 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20250731-arm_cs_fix_clock_v4-v6-4-1dfe10bb3f6f@arm.com

coresight: Introduce pause and resume APIs for source

2025-05-14T10:56:17+00:00

Introduce APIs for pausing and resuming trace source and export as GPL
symbols.

Signed-off-by: Leo Yan 
Reviewed-by: Mike Leach 
Reviewed-by: James Clark 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20250401180708.385396-3-leo.yan@arm.com

coresight: Remove extern from function declarations

2025-04-30T13:58:19+00:00

Function declarations are extern by default so remove the extra noise
and inconsistency.

Reviewed-by: Leo Yan 
Reviewed-by: Yeoreum Yun 
Signed-off-by: James Clark 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20250325-james-coresight-claim-tags-v4-7-dfbd3822b2e5@linaro.org