linux.git/include/linux/clk, branch master

clk: renesas: rzg2l: Remove DSI clock rate restrictions

2026-01-16T09:42:33+00:00

Convert the limited MIPI clock calculations to a full range of settings
based on math including H/W limitation validation.
Since the required DSI division setting must be specified from external
sources before calculations, expose a new API to set it.

Signed-off-by: Chris Brandt 
Reviewed-by: Biju Das 
Tested-by: Biju Das 
Reviewed-by: Hugo Villeneuve 
Tested-by: Hugo Villeneuve 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20251124131003.992554-2-chris.brandt@renesas.com
Signed-off-by: Geert Uytterhoeven

clk: renesas: rzv2h: Add support for DSI clocks

2025-10-27T10:58:03+00:00

Add support for PLLDSI and its post-dividers in the RZ/V2H CPG driver and
export helper APIs for use by the DSI driver.

Introduce per-PLL-DSI state in the CPG private structure and provide a
set of helper functions that find valid PLL parameter combinations for
a requested frequency. The new helpers are rzv2h_get_pll_pars(),
rzv2h_get_pll_div_pars(), rzv2h_get_pll_divs_pars() and
rzv2h_get_pll_dtable_pars() and they are exported in the "RZV2H_CPG"
namespace for use by other consumers (notably the DSI driver). These
helpers perform iterative searches over PLL parameters (M, K, P, S)
and optional post-dividers and return the best match (or an exact
match when possible).

Move PLL/CLK related limits and parameter types into the shared
include (include/linux/clk/renesas.h) by adding struct rzv2h_pll_limits,
struct rzv2h_pll_pars and struct rzv2h_pll_div_pars plus the
RZV2H_CPG_PLL_DSI_LIMITS() helper macro to define DSI PLL limits.

This change centralises the PLLDSI algorithms so the CPG and DSI
drivers compute PLL parameters consistently and allows the DSI driver
to accurately request rates and program its PLL.

Co-developed-by: Fabrizio Castro 
Signed-off-by: Fabrizio Castro 
Signed-off-by: Lad Prabhakar 
Acked-by: Tomi Valkeinen 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20251015192611.241920-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

Merge branch 'clk-determine-rate' into clk-next

2025-10-06T18:02:50+00:00

* clk-determine-rate: (120 commits)
  clk: microchip: core: remove duplicate roclk_determine_rate()
  clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver
  clk: scmi: migrate round_rate() to determine_rate()
  clk: ti: fapll: convert from round_rate() to determine_rate()
  clk: ti: dra7-atl: convert from round_rate() to determine_rate()
  clk: ti: divider: convert from round_rate() to determine_rate()
  clk: ti: composite: convert from round_rate() to determine_rate()
  clk: ti: dpll: convert from round_rate() to determine_rate()
  clk: ti: dpll: change error return from ~0 to -EINVAL
  clk: ti: dpll: remove round_rate() in favor of determine_rate()
  clk: tegra: tegra210-emc: convert from round_rate() to determine_rate()
  clk: tegra: super: convert from round_rate() to determine_rate()
  clk: tegra: pll: convert from round_rate() to determine_rate()
  clk: tegra: periph: divider: convert from round_rate() to determine_rate()
  clk: tegra: divider: convert from round_rate() to determine_rate()
  clk: tegra: audio-sync: convert from round_rate() to determine_rate()
  clk: fixed-factor: drop round_rate() clk ops
  clk: divider: remove round_rate() in favor of determine_rate()
  clk: visconti: pll: convert from round_rate() to determine_rate()
  clk: versatile: vexpress-osc: convert from round_rate() to determine_rate()
  ...

ARM: at91: remove default values for PMC_PLL_ACR

2025-09-17T17:15:32+00:00

Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL and load them from PLL
characteristics structure

Co-developed-by: Andrei Simion 
Signed-off-by: Andrei Simion 
Signed-off-by: Cristian Birsan 
[nicolas.ferre@microchip.com: fix pll acr write sequence, preserve val]
Signed-off-by: Nicolas Ferre

clk: ti: dpll: convert from round_rate() to determine_rate()

2025-09-08T16:50:55+00:00

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate(). Part of these changes were done
using the Coccinelle semantic patch on the cover letter of this
series, and the rest of the changes were manually done.

omap4_dpll_regm4xen_round_rate() is now only called by
omap4_dpll_regm4xen_determine_rate(), so let's merge that functionality
into one function. This is needed for another cleanup to completely
remove the round_rate() clk ops from the clk core.

Tested-by: Anddreas Kemnade  # OMAP3 GTA04, OMAP4 Panda
Reviewed-by: Kevin Hilman 
Tested-by: Kevin Hilman 
Signed-off-by: Brian Masney

clk: davinci: remove support for da830

2025-03-13T20:17:41+00:00

This SoC has some leftover code all over the kernel but no boards are
supported anymore. Remove support for da830 from the davinci clock
driver. With it: remove the ifdefs around the data structures as the
da850 remains the only davinci SoC supported and the only user of this
driver.

Signed-off-by: Bartosz Golaszewski 
Link: https://lore.kernel.org/r/20250304133423.100884-1-brgl@bgdev.pl
Acked-by: David Lechner 
Signed-off-by: Stephen Boyd

clk: ti: Improve clksel clock bit parsing for reg property

2024-02-26T11:08:45+00:00

Because of legacy reasons, the TI clksel composite clocks can have
overlapping reg properties, and use a custom ti,bit-shift property.

For the clksel clocks we can start using of the standard reg property
instead of the custom ti,bit-shift property.

To do this, let's add a ti_clk_get_legacy_bit_shift() helper, and make
ti_clk_get_reg_addr() populate the clock bit offset.

This makes it possible to update the devicetree files to use the reg
property one clock at a time.

Acked-by: Stephen Boyd 
Signed-off-by: Tony Lindgren

clk: mmp: Remove old non-OF clock drivers

2023-08-22T21:13:11+00:00

There are no MMP2, PXA168 or PXA910 boards still using board files which
would use these drivers, so remove them.

Signed-off-by: Duje Mihanović 
Link: https://lore.kernel.org/r/20230804-drop-old-mmp-clk-v1-1-0c07db6cee90@skole.hr
Signed-off-by: Stephen Boyd

ARM: s3c: remove s3c24xx specific hacks

2023-01-16T08:26:05+00:00

A number of device drivers reference CONFIG_ARM_S3C24XX_CPUFREQ or
similar symbols that are no longer available with the platform gone,
though the drivers themselves are still used on newer platforms,
so remove these hacks.

Acked-by: Greg Kroah-Hartman 
Acked-by: Linus Walleij 
Acked-by: Jonathan Cameron 
Acked-by: Daniel Lezcano 
Acked-by: Miquel Raynal 
Acked-by: Ulf Hansson 
Acked-by: Stephen Boyd 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Arnd Bergmann

ARM: davinci: drop DAVINCI_DMxxx references

2023-01-12T09:53:12+00:00

Support for all the dm3xx/dm64xx SoCs is no longer
available, so drop all other references to those.

Acked-by: Stephen Boyd 
Signed-off-by: Arnd Bergmann