linux.git/include/dt-bindings/reset, branch vsnprintf Linux kernel source tree Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2024-11-23T01:02:25+00:00 Linus Torvalds torvalds@linux-foundation.org 2024-11-23T01:02:25+00:00 9f3a2ba62c7226a6604b8aaeb92b5ff906fa4e6b Pull clk updates from Stephen Boyd: "The core framework gained a clk provider helper, a clk consumer helper, and some unit tests for the assigned clk rates feature in DeviceTree. On the vendor driver side, we gained a whole pile of SoC driver support detailed below. The majority in the diffstat is Qualcomm, but there's also quite a few Samsung and Mediatek clk driver additions in here as well. The top vendors is quite common, but the sheer amount of new drivers is uncommon, so I'm anticipating a larger number of fixes for clk drivers this cycle. Core: - devm_clk_bulk_get_all_enabled() to return number of clks acquired - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers - KUnit tests for clk-assigned-rates{,-u64} New Drivers: - Marvell PXA1908 SoC clks - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - MediaTek MT6735 SoC clks - MediaTek MT7620, MT7628 and MT7688 MMC clks - Add a driver for gated fixed rate clocks - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs - Camera, display and video clock controllers for Qualcomm SA8775P SoCs - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P - Global, camera, display, GPU, and video clock controllers for Qualcomm SM8475 SoCs - RTC power domain and Battery Backup Function (VBATTB) clock support for the Renesas RZ/G3S SoC - Qualcomm IPQ9574 alpha PLLs - Support for i.MX91 CCM in the i.MX93 driver - Microchip LAN969X SoC clks - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and reset on Renesas RZ/V2H(P) - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1 - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP Updates: - Convert more clk bindings to YAML - Various clk driver cleanups: NULL checks, add const, etc. - Remove END/NUM #defines that count number of clks in various binding headers - Continue moving reset drivers to drivers/reset via auxiliary bus" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits) clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access clk: Fix invalid execution of clk_set_rate clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider clk: lan966x: make it selectable for ARCH_LAN969X clk: eyeq: add EyeQ6H west fixed factor clocks clk: eyeq: add EyeQ6H central fixed factor clocks clk: eyeq: add EyeQ5 fixed factor clocks clk: eyeq: add fixed factor clocks infrastructure clk: eyeq: require clock index with phandle in all cases clk: fixed-factor: add clk_hw_register_fixed_factor_index() function dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles clk: clk-axi-clkgen: make sure to enable the AXI bus clock dt-bindings: clock: axi-clkgen: include AXI clk clk: mmp: Add Marvell PXA1908 MPMU driver clk: mmp: Add Marvell PXA1908 APMU driver clk: mmp: Add Marvell PXA1908 APBCP driver clk: mmp: Add Marvell PXA1908 APBC driver dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Switch to use struct u32_fract instead of custom one ... 
Pull clk updates from Stephen Boyd:
 "The core framework gained a clk provider helper, a clk consumer
  helper, and some unit tests for the assigned clk rates feature in
  DeviceTree. On the vendor driver side, we gained a whole pile of SoC
  driver support detailed below. The majority in the diffstat is
  Qualcomm, but there's also quite a few Samsung and Mediatek clk driver
  additions in here as well. The top vendors is quite common, but the
  sheer amount of new drivers is uncommon, so I'm anticipating a larger
  number of fixes for clk drivers this cycle.

  Core:
   - devm_clk_bulk_get_all_enabled() to return number of clks acquired
   - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers
   - KUnit tests for clk-assigned-rates{,-u64}

  New Drivers:
   - Marvell PXA1908 SoC clks
   - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver
   - TWL6030 clk driver
   - Nuvoton Arbel BMC NPCM8XX SoC clks
   - MediaTek MT6735 SoC clks
   - MediaTek MT7620, MT7628 and MT7688 MMC clks
   - Add a driver for gated fixed rate clocks
   - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs
   - Camera, display and video clock controllers for Qualcomm SA8775P
     SoCs
   - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm
     SAR2130P
   - Global, camera, display, GPU, and video clock controllers for
     Qualcomm SM8475 SoCs
   - RTC power domain and Battery Backup Function (VBATTB) clock support
     for the Renesas RZ/G3S SoC
   - Qualcomm IPQ9574 alpha PLLs
   - Support for i.MX91 CCM in the i.MX93 driver
   - Microchip LAN969X SoC clks
   - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and
     reset on Renesas RZ/V2H(P)
   - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1
   - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP

  Updates:
   - Convert more clk bindings to YAML
   - Various clk driver cleanups: NULL checks, add const, etc.
   - Remove END/NUM #defines that count number of clks in various
     binding headers
   - Continue moving reset drivers to drivers/reset via auxiliary bus"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits)
  clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access
  clk: Fix invalid execution of clk_set_rate
  clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider
  clk: lan966x: make it selectable for ARCH_LAN969X
  clk: eyeq: add EyeQ6H west fixed factor clocks
  clk: eyeq: add EyeQ6H central fixed factor clocks
  clk: eyeq: add EyeQ5 fixed factor clocks
  clk: eyeq: add fixed factor clocks infrastructure
  clk: eyeq: require clock index with phandle in all cases
  clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
  dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
  dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
  clk: clk-axi-clkgen: make sure to enable the AXI bus clock
  dt-bindings: clock: axi-clkgen: include AXI clk
  clk: mmp: Add Marvell PXA1908 MPMU driver
  clk: mmp: Add Marvell PXA1908 APMU driver
  clk: mmp: Add Marvell PXA1908 APBCP driver
  clk: mmp: Add Marvell PXA1908 APBC driver
  dt-bindings: clock: Add Marvell PXA1908 clock bindings
  clk: mmp: Switch to use struct u32_fract instead of custom one
  ...
Merge branches 'clk-marvell', 'clk-adi', 'clk-qcom' and 'clk-devm' into clk-next 2024-11-19T04:01:35+00:00 Stephen Boyd sboyd@kernel.org 2024-11-19T04:01:35+00:00 21a5352dc702d8e6dc874e0eb6ba6d81291a788a - Add devm_clk_bulk_get_all_enabled() to return number of clks acquired - Marvell PXA1908 SoC clks * clk-marvell: clk: mmp: Add Marvell PXA1908 MPMU driver clk: mmp: Add Marvell PXA1908 APMU driver clk: mmp: Add Marvell PXA1908 APBCP driver clk: mmp: Add Marvell PXA1908 APBC driver dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Switch to use struct u32_fract instead of custom one * clk-adi: clk: clk-axi-clkgen: make sure to enable the AXI bus clock dt-bindings: clock: axi-clkgen: include AXI clk * clk-qcom: (43 commits) clk: qcom: remove unused data from gcc-ipq5424.c clk: qcom: Add support for Global Clock Controller on QCS8300 dt-bindings: clock: qcom: Add GCC clocks for QCS8300 clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574 dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding clk: qcom: add SAR2130P GPU Clock Controller support clk: qcom: dispcc-sm8550: enable support for SAR2130P clk: qcom: tcsrcc-sm8550: add SAR2130P support clk: qcom: add support for GCC on SAR2130P clk: qcom: rpmh: add support for SAR2130P clk: qcom: rcg2: add clk_rcg2_shared_floor_ops dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible dt-bindings: clock: qcom: document SAR2130P Global Clock Controller dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible clk: qcom: Make GCC_6125 depend on QCOM_GDSC dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros ... * clk-devm: clk: Provide devm_clk_bulk_get_all_enabled() helper 
 - Add devm_clk_bulk_get_all_enabled() to return number of clks acquired
 - Marvell PXA1908 SoC clks

* clk-marvell:
  clk: mmp: Add Marvell PXA1908 MPMU driver
  clk: mmp: Add Marvell PXA1908 APMU driver
  clk: mmp: Add Marvell PXA1908 APBCP driver
  clk: mmp: Add Marvell PXA1908 APBC driver
  dt-bindings: clock: Add Marvell PXA1908 clock bindings
  clk: mmp: Switch to use struct u32_fract instead of custom one

* clk-adi:
  clk: clk-axi-clkgen: make sure to enable the AXI bus clock
  dt-bindings: clock: axi-clkgen: include AXI clk

* clk-qcom: (43 commits)
  clk: qcom: remove unused data from gcc-ipq5424.c
  clk: qcom: Add support for Global Clock Controller on QCS8300
  dt-bindings: clock: qcom: Add GCC clocks for QCS8300
  clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC
  clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
  dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding
  clk: qcom: add SAR2130P GPU Clock Controller support
  clk: qcom: dispcc-sm8550: enable support for SAR2130P
  clk: qcom: tcsrcc-sm8550: add SAR2130P support
  clk: qcom: add support for GCC on SAR2130P
  clk: qcom: rpmh: add support for SAR2130P
  clk: qcom: rcg2: add clk_rcg2_shared_floor_ops
  dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles
  dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible
  dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible
  dt-bindings: clock: qcom: document SAR2130P Global Clock Controller
  dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible
  clk: qcom: Make GCC_6125 depend on QCOM_GDSC
  dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros
  dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros
  ...

* clk-devm:
  clk: Provide devm_clk_bulk_get_all_enabled() helper
dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers 2024-11-14T20:52:14+00:00 Yassine Oudjana y.oudjana@protonmail.com 2024-11-06T11:14:30+00:00 a7479860bb4099a8eef64999e843c085838248e4 Add device tree bindings for syscon clock and reset controllers (IMGSYS, MFGCFG, VDECSYS and VENCSYS). Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241106111402.200940-2-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add device tree bindings for syscon clock and reset controllers (IMGSYS,
MFGCFG, VDECSYS and VENCSYS).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241106111402.200940-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Merge branch '20241028060506.246606-3-quic_srichara@quicinc.com' into clk-for-6.13 2024-11-06T00:33:17+00:00 Bjorn Andersson andersson@kernel.org 2024-11-06T00:33:17+00:00 153986098c6639b3b07b3e49fc33af3109d18594 Merge IPQ5424 global clock controller binding through topic branch to make the constants available for both clock and DeviceTree branches. 
Merge IPQ5424 global clock controller binding through topic branch to
make the constants available for both clock and DeviceTree branches.
dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding 2024-11-06T00:32:44+00:00 Sricharan Ramabadhran quic_srichara@quicinc.com 2024-10-28T06:05:02+00:00 03e525c66de2535dc1afd26be004621c7c5a253e Add binding for the Qualcomm IPQ5424 Global Clock Controller Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241028060506.246606-3-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Add binding for the Qualcomm IPQ5424 Global Clock Controller

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241028060506.246606-3-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles 2024-11-06T00:21:11+00:00 Konrad Dybcio konrad.dybcio@linaro.org 2024-10-27T01:24:44+00:00 111481020aa599764790c807312465a4c94f4b5c Expand qcom,sm8450-gpucc bindings to include SAR2130P. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-5-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> 
Expand qcom,sm8450-gpucc bindings to include SAR2130P.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-5-ecad2a1432ba@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
dt-bindings: mfd: aspeed: Support for AST2700 2024-11-01T16:11:50+00:00 Ryan Chen ryan_chen@aspeedtech.com 2024-10-23T09:01:51+00:00 76c6217c31266e800b67a476bba59dfeb9858a90 Add reset, clk dt bindings headers, and update compatible support for AST2700 clk, silicon-id in yaml. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20241023090153.1395220-2-ryan_chen@aspeedtech.com Signed-off-by: Lee Jones <lee@kernel.org> 
Add reset, clk dt bindings headers, and update compatible
support for AST2700 clk, silicon-id in yaml.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20241023090153.1395220-2-ryan_chen@aspeedtech.com
Signed-off-by: Lee Jones <lee@kernel.org>
dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings 2024-10-17T19:24:35+00:00 Yassine Oudjana y.oudjana@protonmail.com 2024-10-17T07:17:05+00:00 ea1cca026842bc83af92785e61a4433bcc71ea70 Add clock definitions for the main clock and reset controllers of MT6735 (apmixedsys, topckgen, infracfg and pericfg). Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add clock definitions for the main clock and reset controllers of MT6735
(apmixedsys, topckgen, infracfg and pericfg).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: clock, reset: fix top-comment indentation rk3576 headers 2024-09-09T23:13:05+00:00 Heiko Stuebner heiko@sntech.de 2024-09-09T22:31:49+00:00 eb3b3f520518003cd363239fc160bdd7ed327319 Block comments should align the * on each line, as checkpatch rightfully pointed out, so fix that style issue on the newly added rk3576 headers. Fixes: 49c04453db81 ("dt-bindings: clock, reset: Add support for rk3576") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240909223149.85364-1-heiko@sntech.de Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Block comments should align the * on each line, as checkpatch rightfully
pointed out, so fix that style issue on the newly added rk3576 headers.

Fixes: 49c04453db81 ("dt-bindings: clock, reset: Add support for rk3576")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20240909223149.85364-1-heiko@sntech.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: clock, reset: Add support for rk3576 2024-08-29T08:28:16+00:00 Detlev Casanova detlev.casanova@collabora.com 2024-08-28T15:42:50+00:00 49c04453db81fc806906e26ef9fc53bdb635ff39 Add clock and reset ID defines for rk3576. Compared to the downstream bindings written by Elaine, this uses continous gapless IDs starting at 0. Thus all numbers are different between downstream and upstream, but names are kept exactly the same. Also add documentation for the rk3576 CRU core. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/0102019199a76766-f3a2b53f-d063-458b-b0d1-dfbc2ea1893c-000000@eu-west-1.amazonses.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> 
Add clock and reset ID defines for rk3576.

Compared to the downstream bindings written by Elaine, this uses
continous gapless IDs starting at 0. Thus all numbers are
different between downstream and upstream, but names are kept
exactly the same.

Also add documentation for the rk3576 CRU core.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/0102019199a76766-f3a2b53f-d063-458b-b0d1-dfbc2ea1893c-000000@eu-west-1.amazonses.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>