linux.git/include/dt-bindings/pinctrl/at91.h, branch vsnprintf

pinctrl: at91: Enable slewrate by default on SAM9X60

2019-11-03T22:34:47+00:00

On SAM9X60, slewrate should be enabled on pins with a switching frequency
below 50Mhz. Since most of our pins do not exceed this value, we enable
slewrate by default. Pins with a switching value that exceeds 50Mhz will
have to explicitly disable slewrate.

This patch changes the ABI. However, the slewrate macros are only used
by SAM9X60 and, at this moment, there are no device-tree files available
for this platform.

Suggested-by: Ludovic Desroches 
Signed-off-by: Codrin Ciubotariu 
Link: https://lore.kernel.org/r/20191101092031.24896-1-codrin.ciubotariu@microchip.com
Acked-by: Ludovic Desroches 
Reviewed-by: Claudiu Beznea 
Signed-off-by: Linus Walleij

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 498

2019-06-19T15:09:53+00:00

Based on 1 normalized pattern(s):

  gplv2 only

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Kate Stewart 
Reviewed-by: Enrico Weigelt 
Reviewed-by: Armijn Hemel 
Reviewed-by: Allison Randal 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.666840552@linutronix.de
Signed-off-by: Greg Kroah-Hartman

pinctrl: at91: add slewrate support for SAM9X60

2019-02-08T12:07:03+00:00

Add slew rate support for SAM9X60 pin controller.

Signed-off-by: Claudiu Beznea 
Acked-by: Ludovic Desroches 
Signed-off-by: Linus Walleij

pinctrl: at91-pio4: add support for drive strength

2018-07-16T12:46:11+00:00

Add support for the drive strength configuration. Usually, this value is
expressed in mA. Since the numeric value depends on VDDIOP voltage, a
value we can't retrieve at runtime, the controller uses low, medium and
high to define the drive strength.

The PIO controller accepts two values for the low drive configuration: 0
and 1. Most of the time, we don't care about the drive strength. So we
keep the default value which is 0. The drive strength is advertised
through the sysfs only when it has been explicitly set in the device
tree i.e. if its value is different from 0.

Signed-off-by: Ludovic Desroches 
Acked-by: Rob Herring 
Signed-off-by: Linus Walleij

pinctrl: at91: add support for OUTPUT config

2016-10-31T08:16:46+00:00

Add support for pin output control through the pinctrl config:
 - support enabling/disabling output on a given pin
 - support output level setting (high or low)

Signed-off-by: Boris BREZILLON 
Acked-by: Nicolas Ferre 
Signed-off-by: Wenyou Yang 
Signed-off-by: Linus Walleij

pinctrl: at91: add drive strength configuration

2014-09-05T08:32:06+00:00

The SAMA5 and SAM9x5 series both have drive strength
options for the PIOs. This patch adds the ability to set
one of three hardware options for drive strengths of low,
medium or high for the each pin. The actual current output
of the chip based on the setting is defined in the datasheets
and varies per pins separate from banks and with supply
voltage.

This patch adds three new dt-bindings that allow setting the
strength when configuring pins. By default, no change will
be made to the drive strength of a pin from its reset value.
Due to the difference between the register addresses of the
SAMA5 and SAM9x5 series, a new sama5d3-pinctrl id was added.

Signed-off-by: Marek Roszko 
Acked-by: Nicolas Ferre 
Signed-off-by: Linus Walleij

pinctrl: at91: fix typos

2013-09-27T12:10:09+00:00

Fix AT91_PINCTRL_DEBOUNCE_VAL dt macro typo.
Fix at91_pinctrl_mux_ops callback typos.

Signed-off-by: Boris BREZILLON 
Acked-by: Jean-Christophe PLAGNIOL-VILLARD 
Signed-off-by: Linus Walleij

ARM: at91: dt: add pinctrl pre-processor define

2013-05-17T09:34:39+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD 
Acked-by: Linus Walleij 
Signed-off-by: Nicolas Ferre