linux.git/include/dt-bindings/gpio, branch v6.5 Linux kernel source tree dt-bindings: gpio: Remove FSI domain ports on Tegra234 2023-06-06T12:38:58+00:00 Prathamesh Shete pshete@nvidia.com 2023-05-30T10:51:08+00:00 12382ad05110b569d95d29c637e16bbeb115acca Ports S, T, U and V are in a separate controller that is part of the FSI domain. Remove their definitions from the MAIN controller definitions to get rid of the confusion. This technically breaks ABI compatibility with old device trees. However it doesn't cause issues in practice. The GPIO pins impacted by this are used for non-critical functionality. Fixes: a8b10f3d12cfc ("dt-bindings: gpio: Add Tegra234 support") Signed-off-by: Prathamesh Shete <pshete@nvidia.com> [treding@nvidia.com: rewrite commit message] Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Ports S, T, U and V are in a separate controller that is part of the FSI
domain. Remove their definitions from the MAIN controller definitions to
get rid of the confusion.

This technically breaks ABI compatibility with old device trees. However
it doesn't cause issues in practice. The GPIO pins impacted by this are
used for non-critical functionality.

Fixes: a8b10f3d12cfc ("dt-bindings: gpio: Add Tegra234 support")
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
[treding@nvidia.com: rewrite commit message]
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
dt-binding: gpio: publish binding IDs under dual license 2023-01-17T20:43:55+00:00 Etienne Carriere etienne.carriere@linaro.org 2022-09-05T14:55:55+00:00 323b8d0ddb92b189ed7561e8095a9aa43968d519 Changes gpio.h DT binding header file to be published under GPLv2 or BSD-2-Clause license terms. This change allows this GPIO generic bindings header file to be used in software components as bootloaders and OSes that are not published under GPLv2 terms. All contributors to gpio.h file in copy. Cc: Stephen Warren <swarren@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Nuno Sá <nuno.sa@analog.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220905145555.674800-1-etienne.carriere@linaro.org Signed-off-by: Rob Herring <robh@kernel.org> 
Changes gpio.h DT binding header file to be published under GPLv2 or
BSD-2-Clause license terms. This change allows this GPIO generic
bindings header file to be used in software components as bootloaders
and OSes that are not published under GPLv2 terms.

All contributors to gpio.h file in copy.

Cc: Stephen Warren <swarren@nvidia.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Nuno Sá <nuno.sa@analog.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220905145555.674800-1-etienne.carriere@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
dt-bindings: gpio: add pull-disable flag 2022-07-19T08:24:17+00:00 Nuno Sá nuno.sa@analog.com 2022-07-13T13:14:21+00:00 d042656a2170ce1b0d1a72d81a99bc93f0170358 This extends the flags that can be used in GPIO specifiers to indicate that no bias is intended in the pin. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> 
This extends the flags that can be used in GPIO specifiers to indicate
that no bias is intended in the pin.

Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
dt-bindings: gpio: Add a header file for Amlogic Meson S4 2022-01-30T01:52:45+00:00 Qianggui Song qianggui.song@amlogic.com 2022-01-13T03:10:42+00:00 1713a8de4a3bf7d7d2d5759c895e486885fd1cc3 Add a new dt-binding header file which documents the detail pin names. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/20220113031044.2665-3-qianggui.song@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add a new dt-binding header file which documents the detail pin names.

Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/20220113031044.2665-3-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dt-bindings: gpio: Add Tegra241 support 2021-12-23T16:12:11+00:00 Akhil R akhilrajeev@nvidia.com 2021-12-16T14:10:08+00:00 9f01881beae9e40c87f3edfb81e87e973f85d272 Add the port definitions for the main and AON GPIO controllers found on Tegra241 (Grace). Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> 
Add the port definitions for the main and AON GPIO controllers found on
Tegra241 (Grace).

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
dt-bindings: gpio: msc313: Add offsets for ssd20xd 2021-12-20T14:48:43+00:00 Daniel Palmer daniel@0x0f.com 2021-12-13T09:40:33+00:00 e82513696eadcf71048be174b4b71f9903ba4afd Add the gpio offsets for the SSD201 and SSD202D chips. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> 
Add the gpio offsets for the SSD201 and SSD202D chips.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
dt-bindings: gpio: Add Tegra234 support 2021-12-17T11:26:13+00:00 Prathamesh Shete pshete@nvidia.com 2021-12-10T16:02:03+00:00 a8b10f3d12cfc168a389f3d97e1f762732d4d849 Extend the existing Tegra186 GPIO controller device tree bindings with support for the GPIO controller found on Tegra234. The number of pins is slightly different, but the programming model remains the same. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> [treding@nvidia.com: update device tree bindings] Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> 
Extend the existing Tegra186 GPIO controller device tree bindings with
support for the GPIO controller found on Tegra234. The number of pins is
slightly different, but the programming model remains the same.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
[treding@nvidia.com: update device tree bindings]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
dt-bindings: gpio: Add a binding header for the MSC313 GPIO driver 2020-12-05T21:40:28+00:00 Daniel Palmer daniel@0x0f.com 2020-11-29T11:07:58+00:00 588cc1a02633dcc9ee0923d052cd20087e1a6b0a Header adds defines for the gpio number of each pad from the driver view. The gpio block seems to have enough registers for 128 lines but what line is mapped to a physical pin depends on the chip. The gpio block also seems to contain some registers that are not related to gpio but needed somewhere to go. Because of the above the driver itself uses the index of a pin's offset in an array of the possible offsets for a chip as the gpio number. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201129110803.2461700-2-daniel@0x0f.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Header adds defines for the gpio number of each pad from the driver view.

The gpio block seems to have enough registers for 128 lines but what line
is mapped to a physical pin depends on the chip. The gpio block also seems
to contain some registers that are not related to gpio but needed somewhere
to go.

Because of the above the driver itself uses the index of a pin's offset in
an array of the possible offsets for a chip as the gpio number.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201129110803.2461700-2-daniel@0x0f.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dt-bindings: gpio: Use Tegra186-specific include guard 2020-12-05T21:34:12+00:00 Thierry Reding treding@nvidia.com 2020-11-27T14:08:51+00:00 64a38367b45015de42521c4835541f43838caf39 Use a unique include guard for the Tegra186 GPIO DT bindings header to avoid clashes with the DT bindings header for earlier chips. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201127140852.123192-2-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Use a unique include guard for the Tegra186 GPIO DT bindings header to
avoid clashes with the DT bindings header for earlier chips.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201127140852.123192-2-thierry.reding@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: add compatible for Amlogic Meson A1 pin controller 2019-11-04T15:31:34+00:00 Qianggui Song qianggui.song@amlogic.com 2019-10-25T11:49:24+00:00 26f6a7524dd3366eff8cb0e733a856e8d84c6f68 Add new compatible name for Amlogic's Meson-A1 pin controller add a dt-binding header file which document the detail pin names. Note that A1 doesn't need DS bank reg any more, use gpio reg as base. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/1572004167-24150-2-git-send-email-qianggui.song@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add new compatible name for Amlogic's Meson-A1 pin controller
add a dt-binding header file which document the detail pin names.
Note that A1 doesn't need DS bank reg any more, use gpio reg as
base.

Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1572004167-24150-2-git-send-email-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>