linux.git/include/asm-xtensa/sigcontext.h, branch master Linux kernel source tree xtensa: move headers files to arch/xtensa/include 2008-11-06T18:25:09+00:00 Chris Zankel chris@zankel.net 2008-11-06T14:40:46+00:00 367b8112fe2ea5c39a7bb4d263dcdd9b612fae18 Move all header files for xtensa to arch/xtensa/include and platform and variant header files to the appropriate arch/xtensa/platforms/ and arch/xtensa/variants/ directories. Moving the files gets also rid of all uses of symlinks in the Makefile. This has been completed already for the majority of the architectures and xtensa is one out of six missing. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Chris Zankel <chris@zankel.net> 
Move all header files for xtensa to arch/xtensa/include and platform and
variant header files to the appropriate arch/xtensa/platforms/ and
arch/xtensa/variants/ directories.

Moving the files gets also rid of all uses of symlinks in the Makefile.

This has been completed already for the majority of the architectures
and xtensa is one out of six missing.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Chris Zankel <chris@zankel.net>
[XTENSA] Add support for configurable registers and coprocessors 2008-02-14T01:41:43+00:00 Chris Zankel chris@zankel.net 2008-02-12T21:17:07+00:00 c658eac628aa8df040dfe614556d95e6da3a9ffb The Xtensa architecture allows to define custom instructions and registers. Registers that are bound to a coprocessor are only accessible if the corresponding enable bit is set, which allows to implement a 'lazy' context switch mechanism. Other registers needs to be saved and restore at the time of the context switch or during interrupt handling. This patch adds support for these additional states: - save and restore registers that are used by the compiler upon interrupt entry and exit. - context switch additional registers unbound to any coprocessor - 'lazy' context switch of registers bound to a coprocessor - ptrace interface to provide access to additional registers - update configuration files in include/asm-xtensa/variant-fsf Signed-off-by: Chris Zankel <chris@zankel.net> 
The Xtensa architecture allows to define custom instructions and
registers. Registers that are bound to a coprocessor are only
accessible if the corresponding enable bit is set, which allows
to implement a 'lazy' context switch mechanism. Other registers
needs to be saved and restore at the time of the context switch
or during interrupt handling.

This patch adds support for these additional states:

- save and restore registers that are used by the compiler upon
  interrupt entry and exit.
- context switch additional registers unbound to any coprocessor
- 'lazy' context switch of registers bound to a coprocessor
- ptrace interface to provide access to additional registers
- update configuration files in include/asm-xtensa/variant-fsf

Signed-off-by: Chris Zankel <chris@zankel.net>
[XTENSA] Remove oldmask from sigcontext and fix register flush 2008-02-14T01:12:15+00:00 Chris Zankel chris@zankel.net 2008-02-12T20:22:15+00:00 3befce8f0f79be8322aba885ed052b8ad927913d Remove oldmask from the sigcontext structure. Also update wmask and windowstart when we flush the AR registers to stack. Signed-off-by: Chris Zankel <chris@zankel.net> 
Remove oldmask from the sigcontext structure. Also update wmask
and windowstart when we flush the AR registers to stack.

Signed-off-by: Chris Zankel <chris@zankel.net>
[XTENSA] Remove non-rt signal handling 2007-06-01T00:49:32+00:00 Chris Zankel chris@zankel.net 2007-06-01T00:49:32+00:00 29c4dfd92edc26c2cd2c0c64c9201d5b91d6418e The non-rt signal handling was never really used, so we don't break anything. This patch also cleans up the signal stack-frame to make it independent from the processor configuration. It also improves the method used for controlling single-stepping. We now save and restore the 'icountlevel' register that controls single stepping and set or clear the saved state to enable or disable it. Signed-off-by: Chris Zankel <chris@zankel.net> 
The non-rt signal handling was never really used, so we don't break
anything. This patch also cleans up the signal stack-frame to make
it independent from the processor configuration. It also improves
the method used for controlling single-stepping. We now save and
restore the 'icountlevel' register that controls single stepping
and set or clear the saved state to enable or disable it.

Signed-off-by: Chris Zankel <chris@zankel.net>
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 2005-06-24T07:05:22+00:00 Chris Zankel czankel@tensilica.com 2005-06-24T05:01:26+00:00 9a8fd5589902153a134111ed7a40f9cca1f83254 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
The attached patches provides part 6 of an architecture implementation for the
Tensilica Xtensa CPU series.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>