linux.git/include/asm-sh/pgtable.h, branch v2.6.23

sh: Reclaim beginning of P3 space for vmalloc area.

2007-07-25T01:43:47+00:00

The first 1MB of P3 space was reserved and used for page colouring,
as we've reworked that to use fixmaps, we can reclaim the space and
hand it back to VMALLOC_START.

Signed-off-by: Paul Mundt

page table handling cleanup

2007-07-16T16:05:36+00:00

Kill pte_rdprotect(), pte_exprotect(), pte_mkread(), pte_mkexec(), pte_read(),
pte_exec(), and pte_user() except where arch-specific code is making use of
them.

Signed-off-by: Jan Beulich 
Cc: Andi Kleen 
Cc: Christoph Hellwig 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

Clean up mostly unused IOSPACE macros

2007-05-08T18:15:13+00:00

Most architectures defined three macros, MK_IOSPACE_PFN(), GET_IOSPACE()
and GET_PFN() in pgtable.h.  However, the only callers of any of these
macros are in Sparc specific code, either in arch/sparc, arch/sparc64 or
drivers/sbus.

This patch removes the redundant macros from all architectures except
sparc and sparc64.

Signed-off-by: David Gibson 
Cc: 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

sh: Revert lazy dcache writeback changes.

2007-03-05T10:46:47+00:00

These ended up causing too many problems on older parts,
revert for now..

Signed-off-by: Paul Mundt

sh: Revert TLB miss fast-path changes that broke PTEA parts.

2007-02-14T05:13:10+00:00

This ended up causing problems for older parts (particularly ones
using PTEA). Revert this for now, it can be added back in once it's
had some more testing.

Signed-off-by: Paul Mundt

sh: Lazy dcache writeback optimizations.

2007-02-13T01:54:44+00:00

This converts the lazy dcache handling to the model described in
Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
bonus, this slightly cuts down on the cache flushing frequency.

With that and the PTEA handling out of the way, the update_mmu_cache()
implementations can be consolidated, and we no longer have to worry
about which configuration the cache is in for the SH7705 case.

And finally, explicitly disable the lazy writeback on SMP (SH-4A).

Signed-off-by: Paul Mundt

sh: More tidying for large base pages.

2007-02-13T01:54:44+00:00

There were a few more things that needed fixing up, namely THREAD_SIZE
and the TLB miss handler where certain PTRS_PER_PGD == PTRS_PER_PTE
assumptions were being made.

Signed-off-by: Paul Mundt

sh: landisk board build fixes.

2006-12-11T23:42:07+00:00

Get the landisk board building again..

Signed-off-by: Paul Mundt

sh: Reworked swap cache entry encoding for SH-X2 MMU.

2006-12-11T23:42:06+00:00

In the 64-bit PTE case there's no point in restricting the encoding
to the low bits of the PTE, we can instead bump all of this up to
the high 32 bits and extend PTE_FILE_MAX_BITS to 32, adopting the
same convention used by x86 PAE.

There's a minor discrepency between the number of bits used for the
swap type encoding between 32 and 64-bit PTEs, but this is unlikely
to cause any problem given the extended offset.

Signed-off-by: Paul Mundt

sh: Fixup pte_mkhuge() build failure.

2006-12-06T02:20:53+00:00

When hugetlbpage support isn't enabled, this can be bogus.
Wrap it back in _PAGE_FLAGS_HARD to avoid changes to the
base PTE when not aiming for larger sizes.

Signed-off-by: Paul Mundt