linux.git/include/asm-powerpc/reg.h, branch v2.6.22

[POWERPC] pasemi: PA6T oprofile support

2007-04-24T11:31:51+00:00

Oprofile support for PA6T, kernel side.

Also rename the PA6T_SPRN.* defines to SPRN_PA6T.*.

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] pasemi: SMP timebase sync

2007-02-07T03:03:22+00:00

Timebase update is simple on PA6T, since global updates can be done from
one core by writing to an SPR.

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] pasemi: Idle loops

2007-02-07T03:03:22+00:00

Powersave support on PA6T. Right now it only uses 'doze' mode, and
will default to no savings (spin).

Signed-off-by: Olof Johansson 
Acked-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras

[POWERPC] PA6T PMC support

2007-02-07T03:03:19+00:00

Support for PA6T-style PMC registers.

PMCs are completely implementation-dependent on PPC, and PA6T numbers them
differently from the IBM model.

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] Add SPURR SPR to sysfs

2006-12-09T00:39:06+00:00

Now we have a SPURR cpu feature bit, we can export it to userspace in
sysfs.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[POWERPC] Add DSCR SPR to sysfs

2006-12-09T00:39:05+00:00

POWER6 adds a new SPR, the data stream control register (DSCR). It can
be used to adjust how agressive the prefetch mechanisms are.

Its possible we may want to context switch this, but for now just export
it to userspace via sysfs so we can adjust it.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[POWERPC] Cell timebase bug workaround

2006-10-25T01:54:18+00:00

The Cell CPU timebase has an erratum. When reading the entire 64 bits
of the timebase with one mftb instruction, there is a handful of cycles
window during which one might read a value with the low order 32 bits
already reset to 0x00000000 but the high order bits not yet incremeted
by one. This fixes it by reading the timebase again until the low order
32 bits is no longer 0. That might introduce occasional latencies if
hitting mftb just at the wrong time, but no more than 70ns on a cell
blade, and that was considered acceptable.

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] Add 970GX cputable entry

2006-10-23T08:23:17+00:00

970GX cputable entry from Steve Winiecki.

Signed-off-by: Jake Moilanen 

 arch/powerpc/kernel/cputable.c          |   15 +++++++++++++++
 arch/powerpc/oprofile/op_model_power4.c |    2 +-
 include/asm-powerpc/reg.h               |    1 +
 3 files changed, 17 insertions(+), 1 deletion(-)
Signed-off-by: Paul Mackerras

[POWERPC] Update MTFSF_L() comment

2006-10-06T11:10:41+00:00

David Woodhouse points out that the comment accompanying the MTFSF_L
macro is misleading. We should make it clear that the L bit is ignored
on older CPUS, not the entire instruction.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[POWERPC] powerpc: PA6T cputable entry, PVR value

2006-09-13T08:39:52+00:00

Introduce PWRficient PA6T cputable entries and feature bits.

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras