linux.git/include/asm-powerpc/mpic.h, branch v2.6.26

[POWERPC] mpic: Fix use of uninitialized variable

2008-05-23T06:15:37+00:00

Compiling ppc64_defconfig with gcc 4.3 gives thes warnings:

arch/powerpc/sysdev/mpic.c: In function 'mpic_irq_get_priority':
arch/powerpc/sysdev/mpic.c:1351: warning: 'is_ipi' may be used uninitialized in this function
arch/powerpc/sysdev/mpic.c: In function 'mpic_irq_set_priority':
arch/powerpc/sysdev/mpic.c:1328: warning: 'is_ipi' may be used uninitialized in this function

It turns out that in the cases where is_ipi is uninitialized, another
variable (mpic) will be NULL and it is dereferenced.  Protect against
this by returning if mpic is NULL in mpic_irq_set_priority, and removing
mpic_irq_get_priority completely as it has no in tree callers.

This has the nice side effect of making the warning go away.

Signed-off-by: Stephen Rothwell 
Acked-by: Benjamin Herrenschmidt 
Signed-off-by: Paul Mackerras

[POWERPC] pasemi: Distribute interrupts evenly across cpus

2007-12-28T15:22:25+00:00

By default the OpenPIC on PWRficient will bias to one core (since that
will improve changes of the other core being able to stay idle/powered
down). However, this conflicts with most irq load balancing schemes,
since setting an interrupt to be delivered to either core doesn't really
result in the load being shared. It also doesn't work well with the
soft irq disable feature of PPC, since EE will stay on until the first
interrupt is taken while soft disabled.

Set the gconf0 config bit that enables even distribution of interrupts
among the two cores.

Signed-off-by: Olof Johansson

[POWERPC] pasemi: Implement NMI support

2007-12-28T15:22:24+00:00

Some PWRficient-based boards have a NMI button that's wired up to a GPIO
as interrupt source. By configuring the openpic accordingly, these get
delivered as a machine check with high priority, instead of as an external
interrupt.

The device tree contains a property "nmi-source" in the openpic node
for these systems, and it's the (hwirq) source for the input.

Also, for these interrupts, the IACK is read from another register than
the regular (MCACK instead), but they are EOI'd as usual. So implement
said function for the mpic driver.

Finally, move a couple of external function defines to include/ instead
of local under sysdev. Being able to mask/unmask and eoi directly saves
us from setting up a dummy irq handler that will never be called.

Signed-off-by: Olof Johansson

[POWERPC] Update mpic to use dcr_host_t.base

2007-10-03T03:25:27+00:00

Now that dcr_host_t contains the base address, we can use that in the mpic
code, rather than storing it separately.

Signed-off-by: Michael Ellerman 
Acked-by: Benjamin Herrenschmidt 
Signed-off-by: Paul Mackerras

[POWERPC] Add workaround for MPICs with broken register reads

2007-09-13T15:33:25+00:00

Some versions of PWRficient 1682M have an interrupt controller in which
the first register in each pair for interrupt sources doesn't always
read with the right polarity/sense values.

To work around this, keep a software copy of the register instead.  Since
it's not modified from the mpic itself, it's a feasible solution.  Still,
keep it under a config option to avoid wasting memory on other platforms.

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] Add an optional device_node pointer to the irq_host

2007-09-13T15:33:20+00:00

The majority of irq_host implementations (3 out of 4) are associated
with a device_node, and need to stash it somewhere. Rather than having
it somewhere different for each host, add an optional device_node pointer
to the irq_host structure.

Signed-off-by: Michael Ellerman 
Signed-off-by: Paul Mackerras

[POWERPC] MPIC protected sources

2007-07-22T11:30:59+00:00

Some HW platforms, such as the new cell blades, requires some MPIC sources
to be left alone by the operating system. This implements support for
a "protected-sources" property in the mpic controller node containing a list
of source numbers to be protected against operating system interference.

For those interested in the gory details, the MPIC on the southbridge of
those blades has some of the processor outputs routed to the cell, and
at least one routed as a GPIO to the service processor. It will be used
in the GA product for routing some of the southbridge error interrupts
to the service processor which implements some of the RAS stuff, such
as checkstopping when fatal errors occurs before they can propagate.

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras

[POWERPC] MPIC MSI allocator

2007-05-08T03:43:48+00:00

To support MSI on MPIC we need a way to reserve and allocate hardware irq
numbers, this patch implements an allocator for that purpose.

New firmware platforms must define a "msi-available-ranges" property on their
MPIC node for MSI to work. For U3/U4 we do a best-guess setup.

Signed-off-by: Michael Ellerman 
Signed-off-by: Paul Mackerras

[POWERPC] MPIC sys_device & suspend/resume

2007-05-07T10:31:13+00:00

This adds mpic to the system devices and implements suspend
and resume for them.  This is necessary to get interrupts for
modules back to where they were before a suspend to disk.

Signed-off-by: Johannes Berg 
Acked-by: Benjamin Herrenschmidt 
Signed-off-by: Paul Mackerras

[POWERPC] Rename MPIC_BROKEN_U3 to MPIC_U3_HT_IRQS

2007-04-24T12:06:58+00:00

Rename MPIC_BROKEN_U3 to something a little more descriptive. Its
effect is to enable support for HT irqs behind the PCI-X/HT bridge on
U3/U4 (aka. CPC9x5) parts.

Signed-off-by: Michael Ellerman 
Signed-off-by: Paul Mackerras