linux.git/include/asm-powerpc/cputable.h, branch v2.6.23

[POWERPC] Consolidate PowerPC 750 cputable features

2007-07-10T11:55:50+00:00

The 750 CPU_FTR macros have quite a bit of duplication in them.  Consolidate
them to use CPU_FTRS_750 and only list the unique features for derivatives.

Signed-off-by: Josh Boyer 
Signed-off-by: Paul Mackerras

[POWERPC] Merge CPU features pertaining to icache coherency

2007-06-14T12:30:16+00:00

Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially).  It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.

In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).

This tries to clarify the situation a little.  The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified.  We check this, instead of
SPLIT_ID_CACHE nearly everywhere.

The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200.  In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature.  The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.

This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.

Signed-off-by: David Gibson 
Signed-off-by: Paul Mackerras

[POWERPC] Remove CPU_FTR_NEED_COHERENT for 7448.

2007-05-17T11:10:15+00:00

Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx).
This prevents needlessly setting M=1 when not SMP.

Signed-off-by: James.Yang 
Acked-by: Jon Loeliger 
Signed-off-by: Kumar Gala

[POWERPC] pasemi: PA6T oprofile support

2007-04-24T11:31:51+00:00

Oprofile support for PA6T, kernel side.

Also rename the PA6T_SPRN.* defines to SPRN_PA6T.*.

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] Fix PowerPC 750CL and 750GX CPU features

2007-04-24T11:31:47+00:00

PowerPC 750CL has high BATs.  The patch below adds a CPU_FTRS_750CL that
includes that.  Without it, the original firmware mappings in the high BATs
aren't cleared which continue to override the linux translations.

It also adds CPU_FTR_COMMON to CPU_FTRS_750GX for completeness.

Signed-off-by: Josh Boyer 
Signed-off-by: Paul Mackerras

[POWERPC] Add PMC type to cputable

2007-02-07T03:03:19+00:00

Add cputable entries for which type of PMC implementation the processor
has.

I've only filled in the current 64-bit processors, the unfilled default
value will have same behaviour as before so it can be done over time
as needed.

Also tidy up the dummy_perf implementation a bit, aggregating it into
one function with ifdefs instead of several.

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] remove unused CPU_FTRS_POWER6X

2007-02-07T00:57:52+00:00

CPU_FTRS_POWER6X is unused, hence remove it.

Signed-off-by Michael Neuling 

Signed-off-by: Paul Mackerras

Merge branch 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc

2006-12-11T05:31:42+00:00

[POWERPC] Add DSCR SPR to sysfs

2006-12-09T00:39:05+00:00

POWER6 adds a new SPR, the data stream control register (DSCR). It can
be used to adjust how agressive the prefetch mechanisms are.

Its possible we may want to context switch this, but for now just export
it to userspace via sysfs so we can adjust it.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[POWERPC] Add support for FP emulation for the e300c2 core

2006-12-08T08:43:30+00:00

The e300c2 has no FPU.  Its MSR[FP] is grounded to zero.  If an attempt
is made to execute a floating point instruction (including floating-point
load, store, or move instructions), the e300c2 takes a floating-point
unavailable interrupt.

This patch adds support for FP emulation on the e300c2 by declaring a
new CPU_FTR_FP_TAKES_FPUNAVAIL, where FP unavail interrupts are
intercepted and redirected to the ProgramCheck exception path for
correct emulation handling.

(If we run out of CPU_FTR bits we could look to reclaim this bit by adding
support to test the cpu_user_features for PPC_FEATURE_HAS_FPU instead)

It adds a nop to the exception path for 32-bit processors with a FPU.

Signed-off-by: Kim Phillips 
Signed-off-by: Kumar Gala