linux.git/include/asm-mips/hazards.h, branch master Linux kernel source tree MIPS: Move headfiles to new location below arch/mips/include 2008-10-11T15:18:52+00:00 Ralf Baechle ralf@linux-mips.org 2008-09-16T17:48:51+00:00 384740dc49ea651ba350704d13ff6be9976e37fe Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] R1: Fix hazard barriers to make kernels work on R2 also. 2007-10-11T22:46:19+00:00 Ralf Baechle ralf@linux-mips.org 2007-09-21T12:05:44+00:00 572afc248c33c902760f6f24a72c180f0e4f1719 Tested with Malta; inflates malta_defconfig by 3932 bytes. Ideally there should be additional configuration to allow getting rid of this overhead but that would be too much complexity at this stage of the release cycle. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Tested with Malta; inflates malta_defconfig by 3932 bytes.  Ideally there
should be additional configuration to allow getting rid of this overhead
but that would be too much complexity at this stage of the release cycle.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] checkfiles: Fix "need space after that ','" errors. 2007-10-11T22:46:15+00:00 Ralf Baechle ralf@linux-mips.org 2007-10-11T22:46:15+00:00 21a151d8ca3aa74ee79f9791a9d4dc370d3e0636 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Provide empty irq_enable_hazard definition for legacy and R1 cores. 2007-09-10T20:25:28+00:00 Ralf Baechle ralf@linux-mips.org 2007-09-03T14:22:26+00:00 7b0fdaa6a193e0b07d9f72e942f51ce25d9e0387 Following a strict interpretation the empty definition of irq_enable_hazard has always been a bug - but an intentional one because it didn't bite. This has now changed, for uniprocessor kernels mm/slab.c:do_drain() [...] on_each_cpu(do_drain, cachep, 1, 1); check_irq_on(); [...] may be compiled into a mtc0 c0_status; mfc0 c0_status sequence resulting in a back-to-back hazard. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Following a strict interpretation the empty definition of irq_enable_hazard
has always been a bug - but an intentional one because it didn't bite.
This has now changed, for uniprocessor kernels mm/slab.c:do_drain()

[...]
        on_each_cpu(do_drain, cachep, 1, 1);
        check_irq_on();
[...]

may be compiled into a mtc0 c0_status; mfc0 c0_status sequence resulting
in a back-to-back hazard.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Add missing declaration for mips_ihb(). 2007-07-31T20:35:26+00:00 Ralf Baechle ralf@linux-mips.org 2007-07-27T23:49:58+00:00 98de920a2aa4f5939d47cdbb23ebac809308d871 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] SB1: Build fix. 2007-05-11T13:28:31+00:00 Ralf Baechle ralf@linux-mips.org 2007-05-09T16:49:53+00:00 a1b53a7b22934504d8c4e065759e8674e665506d Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] FPU hazard handling 2007-05-11T13:28:31+00:00 Chris Dearman chris@mips.com 2007-05-08T15:09:13+00:00 0b6249567b4ecf6e9d5a8efcf149f3e7cf788cc0 Move FPU hazard handling to hazards.h and provide proper support for MIPSR2 processors Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Move FPU hazard handling to hazards.h and provide proper support for
MIPSR2 processors

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Fix pipeline hazard. 2007-03-24T17:01:49+00:00 Ralf Baechle ralf@linux-mips.org 2007-03-20T13:56:50+00:00 7605b3906192a171e651076325b1ed1d5ea57ec9 In the the sequence: ei .. mfc0 $x, $status the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the kernel code because we knew this was a safe thing to do on all R2 silicon so far but new silicon is changing this. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] vr41xx: need one more nop with mtc0_tlbw_hazard() 2007-01-24T19:23:21+00:00 Yoichi Yuasa yoichi_yuasa@tripeaks.co.jp 2007-01-24T13:22:06+00:00 3f3183709feb35c30ca5f649224d01921870f81c NEC VR4111 and VR4121 need one more nop with mtc0_tlbw_hazard(). Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
NEC VR4111 and VR4121 need one more nop with mtc0_tlbw_hazard().

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] s/__ASSEMBLER__/__ASSEMBLY__/ for clarity sake. 2006-09-27T12:37:57+00:00 Ralf Baechle ralf@linux-mips.org 2006-09-25T14:49:49+00:00 36396f3c36b04f79438f87a0fccfa76aa3de6af9 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>