linux.git/include/asm-mips/cpu.h, branch v2.6.24 Linux kernel source tree [MIPS] Convert list of CPU types from #define to enum. 2007-10-11T22:46:16+00:00 Ralf Baechle ralf@linux-mips.org 2007-10-11T22:46:16+00:00 36cfbaad815908f54872a7b471e9a7a09b4084a4 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 2007-10-11T22:46:05+00:00 Ralf Baechle ralf@linux-mips.org 2007-10-11T22:46:05+00:00 641e97f318870921d048154af6807e46e43c307a It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Add support for BCM47XX CPUs. 2007-10-11T22:46:02+00:00 Aurelien Jarno aurelien@aurel32.net 2007-09-25T13:40:12+00:00 1c0c13eb935c95fd2ca0b0aca6dd4860487fb242 Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Note that the BCM4710 does not support the wait instruction, this
is not a mistake in the code.
    
It originally comes from the OpenWrt patches.
    
Cc: Michael Buesch <mb@bu3sch.de>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Florian Schirmer <jolt@tuxbox.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] PMC MSP71xx mips common 2007-07-10T16:33:03+00:00 Marc St-Jean stjeanma@pmc-sierra.com 2007-06-14T21:55:31+00:00 9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Patch to add mips common support for the PMC-Sierra MSP71xx devices.

Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 2007-07-10T16:33:02+00:00 Fuxin Zhang zhangfx@lemote.com 2007-06-06T06:52:43+00:00 2a21c7300b53b744d16903256a172d9cbcfdd03e Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Enable support for the userlocal hardware register 2007-07-10T16:33:02+00:00 Ralf Baechle ralf@linux-mips.org 2007-07-10T16:33:02+00:00 a36920200c5b89d56120a5e839fe4a603d51b16c Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Which will cut down the cost of RDHWR $29 which is used to obtain the
TLS pointer and so far being emulated in software down to a single cycle
operation.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Add macros to encode processor revisions. 2007-07-06T15:17:11+00:00 Ralf Baechle ralf@linux-mips.org 2007-07-06T13:40:05+00:00 fde97822a295da9dffa4af643b49a58ffc4516ad Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Older processors used to encode processor version and revision in two
4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
have switched to use the 8-bits as 3:3:2 bitfield with the last field as
the patch number.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Use the proper technical term for naming some of the cache macros. 2006-07-13T20:26:04+00:00 Ralf Baechle ralf@linux-mips.org 2006-07-06T12:04:01+00:00 fc5d2d279ff820172a698706d33e733d4578bd6c Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Treat R14000 like R10000. 2006-05-31T23:28:35+00:00 Kumba kumba@gentoo.org 2006-05-17T02:23:59+00:00 44d921b246923380f26b8010e47ac5dfe48fcec5 Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Fix detection and handling of the 74K processor. 2006-05-31T23:28:30+00:00 Chris Dearman chris@mips.com 2006-05-02T13:08:46+00:00 c620953c32d301c2a7bc73f9f780301e110b7d7c Nothing exciting; Linux just didn't know it yet so this is most adding a value to a case statement. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
    
Nothing exciting; Linux just didn't know it yet so this is most adding
a value to a case statement.
    
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>