linux.git/include/asm-arm/system.h, branch v2.6.17

[PATCH] ARM: Fix XScale PMD setting

2006-05-31T23:27:44+00:00

The ARM Architecture Reference Manual lists bit 4 of the PMD as "implementation
defined" and it must be set to zero on Intel XScale CPUs or the cache does
not behave properly. Found by Mike Rapoport while debugging a flash issue
on the PXA255:

	http://marc.10east.com/?l=linux-arm-kernel&m=114845287600782&w=1

Signed-off-by: Deepak Saxena 
Signed-off-by: Linus Torvalds

[ARM] 3377/2: add support for intel xsc3 core

2006-03-28T20:00:40+00:00

Patch from Lennert Buytenhek

This patch adds support for the new XScale v3 core.  This is an
ARMv5 ISA core with the following additions:

- L2 cache
- I/O coherency support (on select chipsets)
- Low-Locality Reference cache attributes (replaces mini-cache)
- Supersections (v6 compatible)
- 36-bit addressing (v6 compatible)
- Single instruction cache line clean/invalidate
- LRU cache replacement (vs round-robin)

I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
cores have separate errata and have to handle things like L2, so it
is simpler to keep it separate.

L2 cache support is currently a build option because the L2 enable
bit must be set before we enable the MMU and there is no easy way to
capture command line parameters at this point.

There are still optimizations that can be done such as using LLR for
copypage (in theory using the exisiting mini-cache code) but those
can be addressed down the road.

Signed-off-by: Deepak Saxena 
Signed-off-by: Lennert Buytenhek 
Signed-off-by: Russell King

[ARM] 3364/1: [cleanup] warning fix - definitions for enable_hlt and disable_hlt

2006-03-15T23:17:26+00:00

Patch from Ben Dooks

The enable_hlt and disable_hlt should be declared in
include/asm/setup.h. This fixes sparse errors from
arch/arm/kernel/process.c

Signed-off-by: Ben Dooks 
Signed-off-by: Russell King

[PATCH] arm: task_thread_info()

2006-01-12T17:08:55+00:00

Signed-off-by: Al Viro 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] sched: add cacheflush() asm

2006-01-12T17:08:49+00:00

Add per-arch sched_cacheflush() which is a write-back cacheflush used by
the migration-cost calibration code at bootup time.

Signed-off-by: Ingo Molnar 
Cc: Nick Piggin 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[ARM] No need to include asm/proc-fns.h into asm/system.h

2005-11-16T18:36:49+00:00

In the old days when arm26/arm32 was combined into the same
architecture, proc-fns.h provided the xchg implementation for
arm26 CPUs.  Since we no longer combine these two, this include
is no longer required.  Remove it.

Signed-off-by: Russell King

[PATCH] ARM SMP: Add ARMv6 memory barriers

2005-07-26T18:44:26+00:00

Convert explicit gcc asm-based memory barriers into smp_mb() calls.
These change between barrier() and the ARMv6 data memory barrier
instruction depending on whether ARMv6 SMP is enabled.

Signed-off-by: Russell King

[PATCH] ARM SMP: Use exclusive load/store for __xchg

2005-07-26T18:39:31+00:00

Signed-off-by: Russell King

[PATCH] ARM: Don't try to send a signal to pid0

2005-06-30T10:06:49+00:00

If we receive an unrecognised abort during boot, don't try to
send a signal to pid0, but instead report the current state.
This leads to less confusing debug reports.

Signed-off-by: Russell King

[PATCH] ARM SMP: __xchg support

2005-06-28T18:22:25+00:00

This enables the existing __xchg implementation to be used on SMP.

Signed-off-by: Russell King