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<title>linux.git/drivers/usb/dwc3, branch v5.10</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>Merge tag 'fixes-for-v5.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-linus</title>
<updated>2020-11-02T12:36:11+00:00</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2020-11-02T12:36:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=58d51f330e76cd7536d1f7e6ef46dd241a7b38ef'/>
<id>58d51f330e76cd7536d1f7e6ef46dd241a7b38ef</id>
<content type='text'>
Felipe writes:

USB: fixes for v5.10-rc2

Nothing major as of yet, we're adding support for Intel Alder Lake-S
in dwc3, together with a few fixes that are quite important (memory
leak in raw-gadget, probe crashes in goku_udc, and so on).

Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;

* tag 'fixes-for-v5.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb:
  usb: raw-gadget: fix memory leak in gadget_setup
  usb: dwc2: Avoid leaving the error_debugfs label unused
  usb: dwc3: ep0: Fix delay status handling
  usb: gadget: fsl: fix null pointer checking
  usb: gadget: goku_udc: fix potential crashes in probe
  usb: dwc3: pci: add support for the Intel Alder Lake-S
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<pre>
Felipe writes:

USB: fixes for v5.10-rc2

Nothing major as of yet, we're adding support for Intel Alder Lake-S
in dwc3, together with a few fixes that are quite important (memory
leak in raw-gadget, probe crashes in goku_udc, and so on).

Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;

* tag 'fixes-for-v5.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb:
  usb: raw-gadget: fix memory leak in gadget_setup
  usb: dwc2: Avoid leaving the error_debugfs label unused
  usb: dwc3: ep0: Fix delay status handling
  usb: gadget: fsl: fix null pointer checking
  usb: gadget: goku_udc: fix potential crashes in probe
  usb: dwc3: pci: add support for the Intel Alder Lake-S
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: fix kernel-doc markups</title>
<updated>2020-10-28T12:18:56+00:00</updated>
<author>
<name>Mauro Carvalho Chehab</name>
<email>mchehab+huawei@kernel.org</email>
</author>
<published>2020-10-23T16:33:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=cbdc0f54560f94c2205ddbebb5464d65868af0d8'/>
<id>cbdc0f54560f94c2205ddbebb5464d65868af0d8</id>
<content type='text'>
There is a common comment marked, instead, with kernel-doc
notation.

Also, some identifiers have different names between their
prototypes and the kernel-doc markup.

Signed-off-by: Mauro Carvalho Chehab &lt;mchehab+huawei@kernel.org&gt;
Acked-by: Felipe Balbi &lt;balbi@kernel.org&gt;
Link: https://lore.kernel.org/r/0b964be3884def04fcd20ea5c12cb90d0014871c.1603469755.git.mchehab+huawei@kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There is a common comment marked, instead, with kernel-doc
notation.

Also, some identifiers have different names between their
prototypes and the kernel-doc markup.

Signed-off-by: Mauro Carvalho Chehab &lt;mchehab+huawei@kernel.org&gt;
Acked-by: Felipe Balbi &lt;balbi@kernel.org&gt;
Link: https://lore.kernel.org/r/0b964be3884def04fcd20ea5c12cb90d0014871c.1603469755.git.mchehab+huawei@kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: dwc3: ep0: Fix delay status handling</title>
<updated>2020-10-27T09:33:53+00:00</updated>
<author>
<name>Thinh Nguyen</name>
<email>Thinh.Nguyen@synopsys.com</email>
</author>
<published>2020-10-22T22:44:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=fa27e2f6c5e674f3f1225f9ca7a7821faaf393bb'/>
<id>fa27e2f6c5e674f3f1225f9ca7a7821faaf393bb</id>
<content type='text'>
If we want to send a control status on our own time (through
delayed_status), make sure to handle a case where we may queue the
delayed status before the host requesting for it (when XferNotReady
is generated). Otherwise, the driver won't send anything because it's
not EP0_STATUS_PHASE yet. To resolve this, regardless whether
dwc-&gt;ep0state is EP0_STATUS_PHASE, make sure to clear the
dwc-&gt;delayed_status flag if dwc3_ep0_send_delayed_status() is called.
The control status can be sent when the host requests it later.

Cc: &lt;stable@vger.kernel.org&gt;
Fixes: d97c78a1908e ("usb: dwc3: gadget: END_TRANSFER before CLEAR_STALL command")
Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If we want to send a control status on our own time (through
delayed_status), make sure to handle a case where we may queue the
delayed status before the host requesting for it (when XferNotReady
is generated). Otherwise, the driver won't send anything because it's
not EP0_STATUS_PHASE yet. To resolve this, regardless whether
dwc-&gt;ep0state is EP0_STATUS_PHASE, make sure to clear the
dwc-&gt;delayed_status flag if dwc3_ep0_send_delayed_status() is called.
The control status can be sent when the host requests it later.

Cc: &lt;stable@vger.kernel.org&gt;
Fixes: d97c78a1908e ("usb: dwc3: gadget: END_TRANSFER before CLEAR_STALL command")
Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: dwc3: pci: add support for the Intel Alder Lake-S</title>
<updated>2020-10-27T07:02:10+00:00</updated>
<author>
<name>Heikki Krogerus</name>
<email>heikki.krogerus@linux.intel.com</email>
</author>
<published>2020-10-06T13:02:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=1384ab4fee12c4c4f8bd37bc9f8686881587b286'/>
<id>1384ab4fee12c4c4f8bd37bc9f8686881587b286</id>
<content type='text'>
This patch adds the necessary PCI ID for Intel Alder Lake-S
devices.

Signed-off-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</content>
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<pre>
This patch adds the necessary PCI ID for Intel Alder Lake-S
devices.

Signed-off-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: dwc3: of-simple: Add compatible string for Intel Keem Bay platform</title>
<updated>2020-10-02T10:29:13+00:00</updated>
<author>
<name>Wan Ahmad Zainie</name>
<email>wan.ahmad.zainie.wan.mohamad@intel.com</email>
</author>
<published>2020-09-21T02:44:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e2c53515b2a63828d226250fd62b38039f613977'/>
<id>e2c53515b2a63828d226250fd62b38039f613977</id>
<content type='text'>
Add compatible string to use this generic glue layer to support
Intel Keem Bay platform's dwc3 controller.

Signed-off-by: Wan Ahmad Zainie &lt;wan.ahmad.zainie.wan.mohamad@intel.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add compatible string to use this generic glue layer to support
Intel Keem Bay platform's dwc3 controller.

Signed-off-by: Wan Ahmad Zainie &lt;wan.ahmad.zainie.wan.mohamad@intel.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: dwc3: gadget: Support up to max stream id</title>
<updated>2020-10-02T10:29:13+00:00</updated>
<author>
<name>Thinh Nguyen</name>
<email>Thinh.Nguyen@synopsys.com</email>
</author>
<published>2020-09-29T22:26:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e0a93d98f488fafd9285ea835539ff58d3ab0438'/>
<id>e0a93d98f488fafd9285ea835539ff58d3ab0438</id>
<content type='text'>
DWC3 IPs can use the maximum stream id (up to 2^16) specified by the
USB 3.x specs. Don't limit to stream id 2^15 only. Note that this does
not reflect the number of concurrent streams the controller handles
internally.

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
DWC3 IPs can use the maximum stream id (up to 2^16) specified by the
USB 3.x specs. Don't limit to stream id 2^15 only. Note that this does
not reflect the number of concurrent streams the controller handles
internally.

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: dwc3: gadget: Return early if no TRB update</title>
<updated>2020-10-02T06:57:46+00:00</updated>
<author>
<name>Thinh Nguyen</name>
<email>Thinh.Nguyen@synopsys.com</email>
</author>
<published>2020-10-01T00:44:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2338484d14f3f4b3bd1f7bb416805976e7bd0cc5'/>
<id>2338484d14f3f4b3bd1f7bb416805976e7bd0cc5</id>
<content type='text'>
If the transfer had already started and there's no TRB to update, then
there's no need to go through __dwc3_gadget_kick_transfer(). There is
no problem reissuing UPDATE_TRANSFER command. This change just saves
the driver from doing a few operations. This happens when we run out of
TRB and function driver still queues for more requests.

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If the transfer had already started and there's no TRB to update, then
there's no need to go through __dwc3_gadget_kick_transfer(). There is
no problem reissuing UPDATE_TRANSFER command. This change just saves
the driver from doing a few operations. This happens when we run out of
TRB and function driver still queues for more requests.

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: dwc3: gadget: Keep TRBs in request order</title>
<updated>2020-10-02T06:57:46+00:00</updated>
<author>
<name>Thinh Nguyen</name>
<email>Thinh.Nguyen@synopsys.com</email>
</author>
<published>2020-10-01T00:44:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=346a15cdf65263d8a8dfdbc5d2702471a2dcef6c'/>
<id>346a15cdf65263d8a8dfdbc5d2702471a2dcef6c</id>
<content type='text'>
If we couldn't finish preparing all the TRBs of a request, don't prepare
the next request. Otherwise, the TRBs order will be mixed up and the
controller will process the wrong TRB. This is a corner case where
there's not enough TRBs for a request that needs the extra TRB but
there's still 1 available TRB in the pool.

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If we couldn't finish preparing all the TRBs of a request, don't prepare
the next request. Otherwise, the TRBs order will be mixed up and the
controller will process the wrong TRB. This is a corner case where
there's not enough TRBs for a request that needs the extra TRB but
there's still 1 available TRB in the pool.

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: dwc3: gadget: Revise setting IOC when no TRB left</title>
<updated>2020-10-02T06:57:46+00:00</updated>
<author>
<name>Thinh Nguyen</name>
<email>Thinh.Nguyen@synopsys.com</email>
</author>
<published>2020-10-01T00:44:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8dbbe48c7a9989c75e39bfb2a886e163fa21660a'/>
<id>8dbbe48c7a9989c75e39bfb2a886e163fa21660a</id>
<content type='text'>
To keep the setting of interrupt-on-completion (IOC) when out of TRBs
consistent and easier to read, the caller of dwc3_prepare_one_trb()
will determine if the TRB must have IOC bit set. This also reduces the
number of times we need to call dwc3_calc_trbs_left(). Note that we only
care about setting IOC from insufficient number of TRBs for SG and not
linear requests (because we don't need to split linear requests).

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
To keep the setting of interrupt-on-completion (IOC) when out of TRBs
consistent and easier to read, the caller of dwc3_prepare_one_trb()
will determine if the TRB must have IOC bit set. This also reduces the
number of times we need to call dwc3_calc_trbs_left(). Note that we only
care about setting IOC from insufficient number of TRBs for SG and not
linear requests (because we don't need to split linear requests).

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: dwc3: gadget: Look ahead when setting IOC</title>
<updated>2020-10-02T06:57:46+00:00</updated>
<author>
<name>Thinh Nguyen</name>
<email>Thinh.Nguyen@synopsys.com</email>
</author>
<published>2020-10-01T00:44:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f9cc581badb144a3dcd841aee2d3bc2d242fcb2f'/>
<id>f9cc581badb144a3dcd841aee2d3bc2d242fcb2f</id>
<content type='text'>
Previously if we run out of TRBs for the last SG entry that requires
an extra TRB, we set interrupt-on-completion (IOC) bit to an already
prepared TRB (i.e. HWO=1). This logic is not clean, and it's not a
typical way to prepare TRB. Also, this prevents showing IOC setup in
tracepoint when __dwc3_prepare_one_trb() is executed. Instead, let's
look ahead when preparing TRB to know whether to set the IOC bit before
the last SG entry. This requires adding a new parameter "must_interrupt"
to dwc3_prepare_one_trb().

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Previously if we run out of TRBs for the last SG entry that requires
an extra TRB, we set interrupt-on-completion (IOC) bit to an already
prepared TRB (i.e. HWO=1). This logic is not clean, and it's not a
typical way to prepare TRB. Also, this prevents showing IOC setup in
tracepoint when __dwc3_prepare_one_trb() is executed. Instead, let's
look ahead when preparing TRB to know whether to set the IOC bit before
the last SG entry. This requires adding a new parameter "must_interrupt"
to dwc3_prepare_one_trb().

Signed-off-by: Thinh Nguyen &lt;Thinh.Nguyen@synopsys.com&gt;
Signed-off-by: Felipe Balbi &lt;balbi@kernel.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
