linux.git/drivers/usb/dwc3/core.c, branch v3.2

usb: dwc3: core: fix cached revision on our structure

2011-12-14T19:59:30+00:00

All our revision macros are defined with the entire
32-bits which we read from GSNPSID register, so we
must cache all 32-bits properly rather than masking
the top 16-bits.

This will fix all revision checks we have on current
driver.

Signed-off-by: Felipe Balbi

usb: Add module.h to various dwc3 drivers

2011-10-04T17:27:28+00:00

These files uses the full set of MODULE_ macros and so need to
include module.h directly.

Signed-off-by: Paul Gortmaker 
Signed-off-by: Greg Kroah-Hartman

usb: dwc3: core: cache GHWPARAMS* registers

2011-10-04T17:25:55+00:00

cache the contents of GHWPARAMS* registers in
our device structure for easy access.

Signed-off-by: Felipe Balbi 
Signed-off-by: Greg Kroah-Hartman

usb: dwc: remove "All rights reserved" statement.

2011-10-04T17:25:52+00:00

Some people think that this line is not compatible with the GPL. The
statement was required due to the Buenos Aires Convention and is now
deprecated. I remove it because it is said that it is pointless nowdays.

Signed-off-by: Sebastian Andrzej Siewior 
Signed-off-by: Felipe Balbi 
Signed-off-by: Greg Kroah-Hartman

usb: dwc3: add module.h to dwc3-omap.c and core.c

2011-09-09T10:03:00+00:00

We need that header because of THIS_MODULE.

Reported-by: Geert Uytterhoeven 
Signed-off-by: Felipe Balbi

usb: dwc3: core: move the core check before soft reset

2011-09-09T10:02:09+00:00

We read the DWC3_GSNPSID register to make sure we got the correct
register offset passed. One of the recent commits moved the soft reset
before this so in case of the wrong offset we end up with "reset timed
out". This patch moves the "id" check before the reset again.

Signed-off-by: Sebastian Andrzej Siewior 
Signed-off-by: Felipe Balbi

usb: Introduce DesignWare USB3 DRD Driver

2011-08-22T23:03:11+00:00

The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.

Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.

The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.

More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.

While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.

[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2

Signed-off-by: Felipe Balbi 
Signed-off-by: Greg Kroah-Hartman