linux.git/drivers/usb/dwc2/params.c, branch v5.17

usb: dwc2: stm32mp15: set otg_rev

2021-10-25T07:20:26+00:00

STM32MP15 complies with the OTG 2.0. Set OTG revision accordingly. It is
useful for the of_usb_update_otg_caps() routine to check and update
otg_rev to the lower value between DT and provided params.

Signed-off-by: Fabrice Gasnier 
Link: https://lore.kernel.org/r/1634133425-25670-5-git-send-email-fabrice.gasnier@foss.st.com
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: add otg_rev and otg_caps information for gadget driver

2021-10-25T07:20:26+00:00

Currently the dwc2 doesn't fill in the 'otg_caps' of usb_gadget structure.
When registering a gadget device (e.g. via configfs), the
usb_otg_descriptor_init() checks the 'otg_caps' and 'otg_rev'. It defaults
to HNP and SRP bmAttributes if unspecified. There may be a mismatch with
what's being set in dwc2 params structure. This result in the descriptors
to be miss-configured in this case.

So replace 'otg_cap' bit field by 'otg_caps' structure, so hnp, srp and
otg_rev' can be configured directly in the params.
It's then provided to the gadget struct. These parameters can be tuned
for each platform. In case it's not set, it will default to current
behavior.

Also add option to setup these from the device tree by calling
of_usb_update_otg_caps(). This provides support for standard properties
such as "otg-rev", "hnp-disable" and "srp-disable" (see usb-drd.yaml).

Signed-off-by: Fabrice Gasnier 
Link: https://lore.kernel.org/r/1634133425-25670-4-git-send-email-fabrice.gasnier@foss.st.com
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: Skip clock gating on Samsung SoCs

2021-07-21T07:50:27+00:00

Commit 0112b7ce68ea ("usb: dwc2: Update dwc2_handle_usb_suspend_intr
function.") changed the way the driver handles power down modes in a such
way that it uses clock gating when no other power down mode is available.

This however doesn't work well on the DWC2 implementation used on the
Samsung SoCs. When a clock gating is enabled, system hangs. It looks that
the proper clock gating requires some additional glue code in the shared
USB2 PHY and/or Samsung glue code for the DWC2. To restore driver
operation on the Samsung SoCs simply skip enabling clock gating mode
until one finds what is really needed to make it working reliably.

Fixes: 0112b7ce68ea ("usb: dwc2: Update dwc2_handle_usb_suspend_intr function.")
Cc: stable 
Acked-by: Krzysztof Kozlowski 
Signed-off-by: Marek Szyprowski 
Link: https://lore.kernel.org/r/20210716050127.4406-1-m.szyprowski@samsung.com
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: params: Fix naming of 'dwc2_get_hwparams()' in the docs

2021-05-27T07:45:27+00:00

Fixes the following W=1 kernel build warning(s):

 drivers/usb/dwc2/params.c:787: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst

Cc: Minas Harutyunyan 
Cc: Greg Kroah-Hartman 
Cc: linux-usb@vger.kernel.org
Acked-by: Minas Harutyunyan 
Signed-off-by: Lee Jones 
Link: https://lore.kernel.org/r/20210526130037.856068-6-lee.jones@linaro.org
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: Enable RPi in ACPI mode

2021-04-22T08:55:54+00:00

The dwc2 driver has everything we need to run
in ACPI mode except for the ACPI module device table
boilerplate. With that added and identified as "BCM2848",
an id in use by other OSs for this device, the dw2
controller on the BCM2711 will work.

Signed-off-by: Jeremy Linton 
Link: https://lore.kernel.org/r/20210413215834.3126447-2-jeremy.linton@arm.com
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: disable Link Power Management on STM32MP15 HS OTG

2021-01-12T11:54:42+00:00

Link Power Management (LPM) on STM32MP15 OTG HS encounters instabilities
with some Host controllers. OTG core fails to exit L1 state in 200us:
"dwc2 49000000.usb-otg: Failed to exit L1 sleep state in 200us."
Then the device is still not enumerated.

To avoid this issue, disable Link Power Management on STM32MP15 HS OTG.

Acked-by: Minas Harutyunyan 
Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20210105094855.30763-4-amelie.delaunay@foss.st.com
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG

2021-01-12T11:54:42+00:00

When the core is in FS host mode, using the FS transceiver, and a Low-Speed
device is connected, transceiver clock is 6Mhz.
So, to support Low-Speed devices, enable support of FS/LS Low Power mode,
so that the PHY supplies a 6 MHz clock during Low-Speed mode.

Acked-by: Minas Harutyunyan 
Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20210105094855.30763-3-amelie.delaunay@foss.st.com
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS

2021-01-12T11:54:42+00:00

STM32MP15 ahbcfg register default value sets Burst length/type (HBSTLEN)
to Single (32-bit accesses on AHB), which is not recommended, according
to STM32MP157 Reference manual [1].
This patch sets Burst length/type (HBSTLEN) so that bus transactions
target 16x32 bit accesses. This improves OTG controller performance.

[1] https://www.st.com/resource/en/reference_manual/dm00327659.pdf, p.3149

Acked-by: Minas Harutyunyan 
Signed-off-by: Amelie Delaunay 
Link: https://lore.kernel.org/r/20210105094855.30763-2-amelie.delaunay@foss.st.com
Signed-off-by: Greg Kroah-Hartman

usb: dwc2: don't use ID/Vbus detection if usb-role-switch on STM32MP15 SoCs

2020-10-02T10:29:13+00:00

If usb-role-switch is present in the device tree, it means that ID and Vbus
signals are not connected to the OTG controller but to an external
component (GPIOs, Type-C controller). In this configuration, usb role
switch is used to force valid sessions on STM32MP15 SoCs.

Acked-by: Minas Harutyunyan 
Acked-by: Martin Blumenstingl 
Signed-off-by: Amelie Delaunay 
Signed-off-by: Felipe Balbi

usb: dwc2: add support for APM82181 USB OTG

2020-10-02T06:57:39+00:00

adds the specific compatible string for the DWC2 IP found in the APM82181
SoCs. The IP is setup correctly through the auto detection... With the
exception of the AHB Burst Size. The default of GAHBCFG_HBSTLEN_INCR4 of
the "snps,dwc2" can cause a system hang when the USB and SATA is used
concurrently. Because the predecessor (PPC460EX (Canyonlands)) already
had the same problem, this SoC can make use of the existing
dwc2_set_amcc_params() function.

Signed-off-by: Christian Lamparter 
Signed-off-by: Felipe Balbi