linux.git/drivers/tty/serial/8250, branch v4.18

serial: 8250_pci: Remove stalled entries in blacklist

2018-06-28T12:34:39+00:00

After the commit

  7d8905d06405 ("serial: 8250_pci: Enable device after we check black list")

pure serial multi-port cards, such as CH355, got blacklisted and thus
not being enumerated anymore. Previously, it seems, blacklisting them
was on purpose to shut up pciserial_init_one() about record duplication.

So, remove the entries from blacklist in order to get cards enumerated.

Fixes: 7d8905d06405 ("serial: 8250_pci: Enable device after we check black list")
Reported-by: Matt Turner 
Cc: Sergej Pupykin 
Cc: Alexandr Petrenko 
Signed-off-by: Andy Shevchenko 
Reviewed-and-Tested-by: Matt Turner 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman

serial: 8250_dw: Fix runtime PM handling

2018-05-14T11:51:12+00:00

When using kgdb, you get an abort when accessing the UART registers.
This is because the driver has already entered runtime PM and so turned
off the bus clock needed to access the registers.

To fix this, set the capability indicating Runtime PM is active while idle.

Signed-off-by: Phil Edworthy 
Signed-off-by: Greg Kroah-Hartman

serial: 8250: omap: Fix idling of clocks for unused uarts

2018-05-14T11:51:12+00:00

I noticed that unused UARTs won't necessarily idle properly always
unless at least one byte tx transfer is done first.

After some debugging I narrowed down the problem to the scr register
dma configuration bits that need to be set before softreset for the
clocks to idle. Unless we do this, the module clkctrl idlest bits
may be set to 1 instead of 3 meaning the clock will never idle and
is blocking deeper idle states for the whole domain.

This might be related to the configuration done by the bootloader
or kexec booting where certain configurations cause the 8250 or
the clkctrl clock to jam in a way where setting of the scr bits
and reset is needed to clear it. I've tried diffing the 8250
registers for the various modes, but did not see anything specific.
So far I've only seen this on omap4 but I'm suspecting this might
also happen on the other clkctrl using SoCs considering they
already have a quirk enabled for UART_ERRATA_CLOCK_DISABLE.

Let's fix the issue by configuring scr before reset for basic dma
even if we don't use it. The scr register will be reset when we do
softreset few lines after, and we restore scr on resume. We should
do this for all the SoCs with UART_ERRATA_CLOCK_DISABLE quirk flag
set since the ones with UART_ERRATA_CLOCK_DISABLE are all based
using clkctrl similar to omap4.

Looks like both OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL
bits are needed for the clkctrl to idle after a softreset.

And we need to add omap4 to also use the UART_ERRATA_CLOCK_DISABLE
for the related workaround to be enabled. This same compatible
value will also be used for omap5.

Fixes: cdb929e4452a ("serial: 8250_omap: workaround errata around idling UART after using DMA")
Cc: Keerthy 
Cc: Matthijs van Duin 
Cc: Sekhar Nori 
Cc: Tero Kristo 
Signed-off-by: Tony Lindgren 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman

serial: 8250: Add missing rxtrig_bytes on Altera 16550 UART

2018-05-14T11:51:11+00:00

The Altera 16550 UART core supports FCR Rx Trigger Level setting,
but the port definition in the driver is missing the rxtrig_bytes
array specifying the trigger levels. Add the array to make the Rx
Trigger Level setting available on this type of 16550 UART.

Signed-off-by: Marek Vasut 
Cc: Thor Thayer 
Signed-off-by: Greg Kroah-Hartman

serial/aspeed-vuart: fix a couple mod_timer() calls

2018-05-14T11:51:11+00:00

The "unthrottle_timeout" is HZ/10 but mod_timer() takes a the actual
jiffie where you want it to timeout, not an offset.

Fixes: 5909c0bf9c7a ("serial/aspeed-vuart: Implement quick throttle mechanism")
Signed-off-by: Dan Carpenter 
Acked-by: Jeremy Kerr 
Signed-off-by: Greg Kroah-Hartman

serial: 8250_of: Add IO space support

2018-05-14T11:48:29+00:00

Currently the 8250_of driver only supports MEM IO type
accesses.

Some development boards (Huawei D03, specifically) require
IO space access for 8250-compatible OF driver support, so
add it.

The modification is quite simple: just set the port iotype
and associated flags depending on the device address
resource type.

Signed-off-by: John Garry 
Signed-off-by: Greg Kroah-Hartman

serial: 8250_early: Setup divider when uartclk is passed

2018-04-25T12:56:12+00:00

device->baud is always non zero value because it is checked already in
early_serial8250_setup() before init_port is called.

Signed-off-by: Michal Simek 
Signed-off-by: Greg Kroah-Hartman

serial/aspeed-vuart: Implement quick throttle mechanism

2018-04-23T08:16:50+00:00

Although we populate the ->throttle and ->unthrottle UART operations,
these may not be called until the ldisc has had a chance to schedule and
check buffer space. This means that we may overflow the flip buffers
without ever hitting the ldisc's throttle threshold.

This change implements an interrupt-based throttle, where we check for
space in the flip buffers before reading characters from the UART's
FIFO. If there's no space available, we disable the RX interrupt and
schedule a timer to check for space later.

For this, we need an unlocked version of the set_throttle function to be
able to change throttle state from the irq_handler, which already holds
port->lock.

This prevents a case where we drop characters under heavy RX load.

Signed-off-by: Jeremy Kerr 
Tested-by: Eddie James 
Tested-by: Joel Stanley 
Signed-off-by: Greg Kroah-Hartman

serial/aspeed-vuart: Implement rx throttling

2018-04-23T08:16:50+00:00

The aspeed VUART runs at LPC bus frequency, rather than being restricted
to a typical UART baud rate. This means that the VUART can receive a lot
of data, which can overrun tty flip buffers, and/or cause a large amount
of interrupt traffic.

This change implements the uart_port->throttle & unthrottle callbacks,
implemented by disabling the receiver line status & received data
available IRQs.

Signed-off-by: Jeremy Kerr 
Tested-by: Eddie James 
Tested-by: Joel Stanley 
Signed-off-by: Greg Kroah-Hartman

serial/8250: export serial8250_read_char

2018-04-23T08:16:50+00:00

Currently, we export serial8250_rx_chars, which does a whole bunch of
reads from the 8250 data register, without any form of flow control
between reads.

An upcoming change to the aspeed vuart driver implements more
fine-grained flow control in the interrupt handler, requiring
character-at-a-time control over the rx path.

This change exports serial8250_read_char to allow this.

Signed-off-by: Jeremy Kerr 
Tested-by: Eddie James 
Tested-by: Joel Stanley 
Signed-off-by: Greg Kroah-Hartman