<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/thunderbolt, branch v6.5-rc2</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>thunderbolt: Add test case for 3 DisplayPort tunnels</title>
<updated>2023-06-16T06:53:29+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2022-02-14T12:09:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=481012b479fe6d8dd4e01d739c359a8d99d074a9'/>
<id>481012b479fe6d8dd4e01d739c359a8d99d074a9</id>
<content type='text'>
Intel Barlow Ridge Thunderbolt controller has 3 DP IN adapters. This
allows 3 simultaneus DisplayPort tunnels through either one or two USB4
downstream ports (in any possible configuration). Add test case for
this.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Intel Barlow Ridge Thunderbolt controller has 3 DP IN adapters. This
allows 3 simultaneus DisplayPort tunnels through either one or two USB4
downstream ports (in any possible configuration). Add test case for
this.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Add DisplayPort 2.x tunneling support</title>
<updated>2023-06-16T06:53:29+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2023-01-23T08:42:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2d7e047297983dd29c29c41b8b7034d64f861aa2'/>
<id>2d7e047297983dd29c29c41b8b7034d64f861aa2</id>
<content type='text'>
This adds support for the UHBR (Ultra High Bit Rate) bandwidths
introduced with DisplayPort 2.0 (and refined in 2.1). These can go up to
80 Gbit/s and their support is represent in additional bits in the DP IN
capability.

This updates the DisplayPort tunneling to support these new rates too.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds support for the UHBR (Ultra High Bit Rate) bandwidths
introduced with DisplayPort 2.0 (and refined in 2.1). These can go up to
80 Gbit/s and their support is represent in additional bits in the DP IN
capability.

This updates the DisplayPort tunneling to support these new rates too.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Make bandwidth allocation mode function names consistent</title>
<updated>2023-06-16T06:53:29+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2023-02-01T11:21:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8d73f6b8e0487ac0ed4acd883a6788b2492a5692'/>
<id>8d73f6b8e0487ac0ed4acd883a6788b2492a5692</id>
<content type='text'>
Make sure the DisplayPort bandwidth allocation mode function names are
consistent with the existing ones, such as USB3.

No functional changes.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make sure the DisplayPort bandwidth allocation mode function names are
consistent with the existing ones, such as USB3.

No functional changes.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Enable CL2 low power state</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2022-11-06T11:07:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=fd4d58d1fef9ae9b0ee235eaad73d2e0a6a73025'/>
<id>fd4d58d1fef9ae9b0ee235eaad73d2e0a6a73025</id>
<content type='text'>
For USB4 v2 routers we can also enable CL2 which allows better power
savings and thermal management than CL0s and CL1.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For USB4 v2 routers we can also enable CL2 which allows better power
savings and thermal management than CL0s and CL1.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Add support for enhanced uni-directional TMU mode</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2022-10-11T09:11:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=d49b4f043d63bddf4c1836623b8ae800878ed2e3'/>
<id>d49b4f043d63bddf4c1836623b8ae800878ed2e3</id>
<content type='text'>
This is new TMU mode introduced with the USB4 v2. This mode is simpler
than the existing ones and allows all CL states as well. Enable this for
all links where both side routers are v2 and keep the existing
functionality for the v1 and earlier links.

Currently only support the MedRes rate. We can add the HiFi rate later
too if it turns out to be useful.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is new TMU mode introduced with the USB4 v2. This mode is simpler
than the existing ones and allows all CL states as well. Enable this for
all links where both side routers are v2 and keep the existing
functionality for the v1 and earlier links.

Currently only support the MedRes rate. We can add the HiFi rate later
too if it turns out to be useful.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Increase NVM_MAX_SIZE to support Intel Barlow Ridge controller</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Gil Fine</name>
<email>gil.fine@linux.intel.com</email>
</author>
<published>2023-05-11T08:19:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=322ff701ffed52fb1cade855b2145a3b4316ccd7'/>
<id>322ff701ffed52fb1cade855b2145a3b4316ccd7</id>
<content type='text'>
Intel Barlow Ridge discrete USB4 controller has larger NOR Flash, hence
increase NVM_MAX_SIZE to support it.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Intel Barlow Ridge discrete USB4 controller has larger NOR Flash, hence
increase NVM_MAX_SIZE to support it.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Move constants related to NVM into nvm.c</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Gil Fine</name>
<email>gil.fine@linux.intel.com</email>
</author>
<published>2023-05-11T08:19:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7c81a578cbd1124265c07895395f0a5f30fab5d1'/>
<id>7c81a578cbd1124265c07895395f0a5f30fab5d1</id>
<content type='text'>
Move constants related to NVM into nvm.c to make the code cleaner. Use a
separate constant for USB4_DATA_DWORDS in usb4.c.

No functional changes.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move constants related to NVM into nvm.c to make the code cleaner. Use a
separate constant for USB4_DATA_DWORDS in usb4.c.

No functional changes.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Limit Intel Barlow Ridge USB3 bandwidth</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2023-05-17T07:45:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f2bfa944080dcbb8eb56259dfd2c07204cbee17e'/>
<id>f2bfa944080dcbb8eb56259dfd2c07204cbee17e</id>
<content type='text'>
Intel Barlow Ridge discrete USB4 host router has the same limitation as
the previous generations so make sure the USB3 bandwidth limitation
quirk is applied to Barlow Ridge too.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Intel Barlow Ridge discrete USB4 host router has the same limitation as
the previous generations so make sure the USB3 bandwidth limitation
quirk is applied to Barlow Ridge too.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Add Intel Barlow Ridge PCI ID</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2022-12-17T06:35:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6f14a210661ce03988ef4ed3c8402037c8e06539'/>
<id>6f14a210661ce03988ef4ed3c8402037c8e06539</id>
<content type='text'>
Intel Barlow Ridge is the first USB4 v2 controller from Intel. The
controller exposes standard USB4 PCI class ID in typical configurations,
however there is a way to configure it so that it uses a special class
ID to allow using s different driver than the Windows inbox one. For
this reason add the Barlow Ridge PCI ID to the Linux driver too so that
the driver can attach regardless of the class ID.

Tested-by: Pengfei Xu &lt;pengfei.xu@intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Intel Barlow Ridge is the first USB4 v2 controller from Intel. The
controller exposes standard USB4 PCI class ID in typical configurations,
however there is a way to configure it so that it uses a special class
ID to allow using s different driver than the Windows inbox one. For
this reason add the Barlow Ridge PCI ID to the Linux driver too so that
the driver can attach regardless of the class ID.

Tested-by: Pengfei Xu &lt;pengfei.xu@intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Fix PCIe adapter capability length for USB4 v2 routers</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Gil Fine</name>
<email>gil.fine@linux.intel.com</email>
</author>
<published>2023-01-25T09:48:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0209c808a56e6469f0ed50dd2e70c3aec074bf90'/>
<id>0209c808a56e6469f0ed50dd2e70c3aec074bf90</id>
<content type='text'>
For USB4 v2 routers, the PCIe adapter capability length is longer.
Display the correct capability length in the debugfs register dump.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For USB4 v2 routers, the PCIe adapter capability length is longer.
Display the correct capability length in the debugfs register dump.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
