<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/thunderbolt/usb4.c, branch v6.8</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>thunderbolt: Fix setting the CNS bit in ROUTER_CS_5</title>
<updated>2024-01-29T07:48:40+00:00</updated>
<author>
<name>Mohammad Rahimi</name>
<email>rahimi.mhmmd@gmail.com</email>
</author>
<published>2024-01-27T03:26:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ec4d82f855ce332de26fe080892483de98cc1a19'/>
<id>ec4d82f855ce332de26fe080892483de98cc1a19</id>
<content type='text'>
The bit 23, CM TBT3 Not Supported (CNS), in ROUTER_CS_5 indicates
whether a USB4 Connection Manager is TBT3-Compatible and should be:
    0b for TBT3-Compatible
    1b for Not TBT3-Compatible

Fixes: b04079837b20 ("thunderbolt: Add initial support for USB4")
Cc: stable@vger.kernel.org
Signed-off-by: Mohammad Rahimi &lt;rahimi.mhmmd@gmail.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The bit 23, CM TBT3 Not Supported (CNS), in ROUTER_CS_5 indicates
whether a USB4 Connection Manager is TBT3-Compatible and should be:
    0b for TBT3-Compatible
    1b for Not TBT3-Compatible

Fixes: b04079837b20 ("thunderbolt: Add initial support for USB4")
Cc: stable@vger.kernel.org
Signed-off-by: Mohammad Rahimi &lt;rahimi.mhmmd@gmail.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Fix minimum allocated USB 3.x and PCIe bandwidth</title>
<updated>2023-12-08T07:03:49+00:00</updated>
<author>
<name>Gil Fine</name>
<email>gil.fine@linux.intel.com</email>
</author>
<published>2023-11-30T16:17:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f0b94c1c5c7994a74e487f43c91cfc922105a423'/>
<id>f0b94c1c5c7994a74e487f43c91cfc922105a423</id>
<content type='text'>
With the current bandwidth allocation we end up reserving too much for the USB
3.x and PCIe tunnels that leads to reduced capabilities for the second
DisplayPort tunnel.

Fix this by decreasing the USB 3.x allocation to 900 Mb/s which then allows
both tunnels to get the maximum HBR2 bandwidth.  This way, the reserved
bandwidth for USB 3.x and PCIe, would be 1350 Mb/s (taking weights of USB 3.x
and PCIe into account). So bandwidth allocations on a link are:
USB 3.x + PCIe tunnels =&gt; 1350 Mb/s
DisplayPort tunnel #1  =&gt; 17280 Mb/s
DisplayPort tunnel #2  =&gt; 17280 Mb/s

Total consumed bandwidth is 35910 Mb/s. So that all the above can be tunneled
on a Gen 3 link (which allows maximum of 36000 Mb/s).

Fixes: 582e70b0d3a4 ("thunderbolt: Change bandwidth reservations to comply USB4 v2")
Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With the current bandwidth allocation we end up reserving too much for the USB
3.x and PCIe tunnels that leads to reduced capabilities for the second
DisplayPort tunnel.

Fix this by decreasing the USB 3.x allocation to 900 Mb/s which then allows
both tunnels to get the maximum HBR2 bandwidth.  This way, the reserved
bandwidth for USB 3.x and PCIe, would be 1350 Mb/s (taking weights of USB 3.x
and PCIe into account). So bandwidth allocations on a link are:
USB 3.x + PCIe tunnels =&gt; 1350 Mb/s
DisplayPort tunnel #1  =&gt; 17280 Mb/s
DisplayPort tunnel #2  =&gt; 17280 Mb/s

Total consumed bandwidth is 35910 Mb/s. So that all the above can be tunneled
on a Gen 3 link (which allows maximum of 36000 Mb/s).

Fixes: 582e70b0d3a4 ("thunderbolt: Change bandwidth reservations to comply USB4 v2")
Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Add support for asymmetric link</title>
<updated>2023-10-20T15:18:01+00:00</updated>
<author>
<name>Gil Fine</name>
<email>gil.fine@linux.intel.com</email>
</author>
<published>2023-08-10T19:37:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=81af2952e60603d12415e1a6fd200f8073a2ad8b'/>
<id>81af2952e60603d12415e1a6fd200f8073a2ad8b</id>
<content type='text'>
USB4 v2 spec defines a Gen 4 link that can operate as an aggregated
symmetric (80/80G) or asymmetric (120/40G). When the link is asymmetric,
the USB4 port on one side of the link operates with three TX lanes and
one RX lane, while the USB4 port on the opposite side of the link
operates with three RX lanes and one TX lane.

Add support for the asymmetric link and provide functions that can be
used to transition the link to asymmetric and back.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Co-developed-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
USB4 v2 spec defines a Gen 4 link that can operate as an aggregated
symmetric (80/80G) or asymmetric (120/40G). When the link is asymmetric,
the USB4 port on one side of the link operates with three TX lanes and
one RX lane, while the USB4 port on the opposite side of the link
operates with three RX lanes and one TX lane.

Add support for the asymmetric link and provide functions that can be
used to transition the link to asymmetric and back.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Co-developed-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Get rid of usb4_usb3_port_actual_link_rate()</title>
<updated>2023-10-13T05:49:13+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2023-08-31T11:15:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=92b8f7a1b1f95fce5dee1a64902cab9f55576748'/>
<id>92b8f7a1b1f95fce5dee1a64902cab9f55576748</id>
<content type='text'>
It turns out there is no need to use the actual link rate when
reclaiming bandwidth for USB 3.x. The reason is that we use consumed
bandwidth which is coming from xHCI when releasing bandwidth (for
example for DisplayPort tunneling) and this can be anything between
1000 Mb/s to maximum, so when reclaiming we can just bump it up back to
maximum instead of actual link rate (which is always &lt;= maximum).

This allows us to get rid of couple of unnecessary lines of code.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
It turns out there is no need to use the actual link rate when
reclaiming bandwidth for USB 3.x. The reason is that we use consumed
bandwidth which is coming from xHCI when releasing bandwidth (for
example for DisplayPort tunneling) and this can be anything between
1000 Mb/s to maximum, so when reclaiming we can just bump it up back to
maximum instead of actual link rate (which is always &lt;= maximum).

This allows us to get rid of couple of unnecessary lines of code.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Make bandwidth allocation mode function names consistent</title>
<updated>2023-06-16T06:53:29+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2023-02-01T11:21:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8d73f6b8e0487ac0ed4acd883a6788b2492a5692'/>
<id>8d73f6b8e0487ac0ed4acd883a6788b2492a5692</id>
<content type='text'>
Make sure the DisplayPort bandwidth allocation mode function names are
consistent with the existing ones, such as USB3.

No functional changes.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make sure the DisplayPort bandwidth allocation mode function names are
consistent with the existing ones, such as USB3.

No functional changes.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Add support for enhanced uni-directional TMU mode</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2022-10-11T09:11:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=d49b4f043d63bddf4c1836623b8ae800878ed2e3'/>
<id>d49b4f043d63bddf4c1836623b8ae800878ed2e3</id>
<content type='text'>
This is new TMU mode introduced with the USB4 v2. This mode is simpler
than the existing ones and allows all CL states as well. Enable this for
all links where both side routers are v2 and keep the existing
functionality for the v1 and earlier links.

Currently only support the MedRes rate. We can add the HiFi rate later
too if it turns out to be useful.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is new TMU mode introduced with the USB4 v2. This mode is simpler
than the existing ones and allows all CL states as well. Enable this for
all links where both side routers are v2 and keep the existing
functionality for the v1 and earlier links.

Currently only support the MedRes rate. We can add the HiFi rate later
too if it turns out to be useful.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Move constants related to NVM into nvm.c</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Gil Fine</name>
<email>gil.fine@linux.intel.com</email>
</author>
<published>2023-05-11T08:19:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7c81a578cbd1124265c07895395f0a5f30fab5d1'/>
<id>7c81a578cbd1124265c07895395f0a5f30fab5d1</id>
<content type='text'>
Move constants related to NVM into nvm.c to make the code cleaner. Use a
separate constant for USB4_DATA_DWORDS in usb4.c.

No functional changes.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move constants related to NVM into nvm.c to make the code cleaner. Use a
separate constant for USB4_DATA_DWORDS in usb4.c.

No functional changes.

Signed-off-by: Gil Fine &lt;gil.fine@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Enable USB4 v2 PCIe TLP/DLLP extended encapsulation</title>
<updated>2023-06-16T06:53:28+00:00</updated>
<author>
<name>Gil Fine</name>
<email>gil.fine@intel.com</email>
</author>
<published>2022-09-29T09:49:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6e19d48ea0d8aeee5688e5718cf2143d281864f3'/>
<id>6e19d48ea0d8aeee5688e5718cf2143d281864f3</id>
<content type='text'>
USB4 v2 spec introduces modified encapsulation of PCIe TLP and DLLP
packets. This improves the PCIe tunneled traffic usage by reducing
overhead. Enable this if both sides of the link support it.

Signed-off-by: Gil Fine &lt;gil.fine@intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
USB4 v2 spec introduces modified encapsulation of PCIe TLP and DLLP
packets. This improves the PCIe tunneled traffic usage by reducing
overhead. Enable this if both sides of the link support it.

Signed-off-by: Gil Fine &lt;gil.fine@intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thunderbolt: Introduce tb_switch_downstream_port()</title>
<updated>2023-06-09T09:07:22+00:00</updated>
<author>
<name>Gil Fine</name>
<email>gil.fine@intel.com</email>
</author>
<published>2022-09-22T22:30:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7ce542219b6323764cb922722b677005404d9b60'/>
<id>7ce542219b6323764cb922722b677005404d9b60</id>
<content type='text'>
Introduce tb_switch_downstream_port() helper function that returns the
downstream port of a parent switch that is connected to the upstream
port of specified switch. From now on, we use it all across the driver
where applicable.

While there fix a whitespace in comment and rename 'downstream' to
'down' to be consistent with the rest of the driver.

Signed-off-by: Gil Fine &lt;gil.fine@intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Introduce tb_switch_downstream_port() helper function that returns the
downstream port of a parent switch that is connected to the upstream
port of specified switch. From now on, we use it all across the driver
where applicable.

While there fix a whitespace in comment and rename 'downstream' to
'down' to be consistent with the rest of the driver.

Signed-off-by: Gil Fine &lt;gil.fine@intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'thunderbolt-for-v6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt into usb-next</title>
<updated>2023-04-19T09:42:44+00:00</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2023-04-19T09:42:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ced7c981f382fc34b941ee3b861d49bdd9180af4'/>
<id>ced7c981f382fc34b941ee3b861d49bdd9180af4</id>
<content type='text'>
Mika writes:

thunderbolt: Changes for v6.4 merge window

This includes following Thunderbolt/USB4 changes for the v6.4 merge
window:

  - Refactoring of DROM read code paths
  - Convert to use SI units from units.h
  - A couple of cleanups

All these have been in linux-next with no reported issues.

* tag 'thunderbolt-for-v6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt:
  thunderbolt: Introduce usb4_port_sb_opcode_err_to_errno() helper
  thunderbolt: Make use of SI units from units.h
  thunderbolt: Get rid of redundant 'else'
  thunderbolt: Refactor DROM reading
  thunderbolt: use `tb_eeprom_get_drom_offset` to discover DROM offset
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Mika writes:

thunderbolt: Changes for v6.4 merge window

This includes following Thunderbolt/USB4 changes for the v6.4 merge
window:

  - Refactoring of DROM read code paths
  - Convert to use SI units from units.h
  - A couple of cleanups

All these have been in linux-next with no reported issues.

* tag 'thunderbolt-for-v6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt:
  thunderbolt: Introduce usb4_port_sb_opcode_err_to_errno() helper
  thunderbolt: Make use of SI units from units.h
  thunderbolt: Get rid of redundant 'else'
  thunderbolt: Refactor DROM reading
  thunderbolt: use `tb_eeprom_get_drom_offset` to discover DROM offset
</pre>
</div>
</content>
</entry>
</feed>
