linux.git/drivers/thunderbolt/tb.c, branch v6.5

thunderbolt: Fix memory leak in tb_handle_dp_bandwidth_request()

2023-08-04T13:17:47+00:00

The memory allocated in tb_queue_dp_bandwidth_request() needs to be
released once the request is handled to avoid leaking it.

Fixes: 6ce3563520be ("thunderbolt: Add support for DisplayPort bandwidth allocation mode")
Cc: stable@vger.kernel.org
Signed-off-by: Mika Westerberg

thunderbolt: Make bandwidth allocation mode function names consistent

2023-06-16T06:53:29+00:00

Make sure the DisplayPort bandwidth allocation mode function names are
consistent with the existing ones, such as USB3.

No functional changes.

Signed-off-by: Mika Westerberg

thunderbolt: Enable CL2 low power state

2023-06-16T06:53:28+00:00

For USB4 v2 routers we can also enable CL2 which allows better power
savings and thermal management than CL0s and CL1.

Signed-off-by: Mika Westerberg

thunderbolt: Add support for enhanced uni-directional TMU mode

2023-06-16T06:53:28+00:00

This is new TMU mode introduced with the USB4 v2. This mode is simpler
than the existing ones and allows all CL states as well. Enable this for
all links where both side routers are v2 and keep the existing
functionality for the v1 and earlier links.

Currently only support the MedRes rate. We can add the HiFi rate later
too if it turns out to be useful.

Signed-off-by: Mika Westerberg

thunderbolt: Add the new USB4 v2 notification types

2023-06-16T06:53:28+00:00

USB4 v2 spec adds a bunch of new notifications that the connection
manager can use instead of polling. While we do not use these yet we
need to ack the ones routers expect to be acked.

Signed-off-by: Mika Westerberg

thunderbolt: Add support for USB4 v2 80 Gb/s link

2023-06-16T06:53:27+00:00

USB4 v2 bumps the per-lane speed up to 40 Gb/s. Also the lanes are
always bonded which gives 80 Gb/s symmetric link (and 120/40 Gb/s
asymmetric). This updates the speed and width of routers and XDomain
connections to support the Gen 4 link. For now we keep the link as is
even if it is already asymmetric.

While there make tb_port_set_link_width() static.

Signed-off-by: Gil Fine 
Signed-off-by: Mika Westerberg

thunderbolt: Disable CL states when a DMA tunnel is established

2023-06-09T09:07:24+00:00

Tunnels between hosts should not have CL states enabled because
otherwise they might enter a low power state without the other end
noticing which causes packets to be lost. For this reason disable all
CL states upon first DMA tunnel creation. Once the last DMA tunnel is
torn down we try to re-enable them.

Signed-off-by: Mika Westerberg

thunderbolt: Check for first depth router in tb.c

2023-06-09T09:07:23+00:00

Currently tb_switch_clx_enable() enables CL states only for the first
depth router. This is something we may want to change in the future and
in addition it is not visible from the calling path at all. For this
reason do the check in the tb.c so it is immediately visible that we
only do this for the first depth router. Fix the kernel-docs
accordingly.

Signed-off-by: Mika Westerberg

thunderbolt: Switch CL states from enum to a bitmask

2023-06-09T09:07:23+00:00

This is more natural and follows the hardware register layout better.
This makes it easier to see which CL states we enable (even though they
should be enabled together). Rename 'clx_mask' to 'clx' everywhere as
this is now always bitmask.

Signed-off-by: Mika Westerberg

thunderbolt: Move CLx enabling into tb_enable_clx()

2023-06-09T09:07:23+00:00

This avoids some duplication and makes the flow slightly easier to
understand. Also follows what we do in tb_enable_tmu().

Signed-off-by: Mika Westerberg