linux.git/drivers/spi, branch v4.20-rc2

Merge tag 'mfd-next-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

2018-10-25T13:19:15+00:00

Pull MFD updates from Lee Jones:
 "New Drivers
   - Add support for USART SPI to AT91*

  New Functionality
   - Add support for Audio CODECs to motorola-cpcap

  Fix-ups
   - DT documentation fix-ups; atmel-usart
   - Staticise functions/structs; spi-at91-usart, arizona-core
   - Constify; ti-lmu
   - Fix memory leaks; menelaus
   - Change device 'wake-up' status; ti_am335x_tscadc, max8997
   - Power Management (suspend/resume) semantic changes; ti_am335x_adc, cros_ec, max8997
   - SPDX churn; sec-core (+ headers), max* (+ headers), intel* (+ headers),
   - Trivial (whitespace, email addresses, alphabetisise); Kconfig, adp5520, intel_soc_pmic_*
   - Build as module; sec-irq
   - Use new %pOFn printk format for device_node.name; max77620
   - Remove unused code; madera
   - Use generic MACROs; intel_msic, intel_soc_pmic_crc
   - Move to GPIOD; ti-lmu
   - Use managed resources; ti-lmu

  Bug Fixes
   - Add missing headers; at91-usart
   - Prevent device from entering low-power mode; arizona-core
   - Poll for BOOT_DONE to avoid still-booting NACK; madera-core
   - Prevent ADC read from shutting down device; mc13xxx-core"

* tag 'mfd-next-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (45 commits)
  mfd: cros_ec: Avoid unneeded internal declaration warning
  mfd: ti-lmu: Use of_device_get_match_data() helper
  mfd: ti-lmu: Use managed resource for everything
  mfd: ti-lmu: Switch to GPIOD
  mfd: ti-lmu: constify mfd_cell tables
  mfd: max8997: Disable interrupt handling for suspend/resume cycle
  mfd: max8997: Enale irq-wakeup unconditionally
  mfd: arizona: Make array mclk_name static, shrinks object size
  MAINTAINERS: Add myself as designated reviewer of Intel MFD PMIC
  mfd: Convert Intel PMIC drivers to use SPDX identifier 1;5201;0c Reduce size of duplicated comments by switching to use SPDX identifier.
  mfd: Sort headers alphabetically for Intel PMIC drivers
  mfd: intel_soc_pmic_bxtwc: Chain power button IRQs as well
  mfd: intel_soc_pmic_crc: Use REGMAP_IRQ_REG() macro
  mfd: intel_soc_pmic_crc: Use DEFINE_RES_IRQ_NAMED() macro
  mfd: intel_msic: Use DEFINE_RES_IRQ() macro
  mfd: motorola-cpcap: Add audio-codec support
  mfd: mc13xxx-core: Fix PMIC shutdown when reading ADC values
  mfd: madera: Remove unused forward reference
  mfd: max77620: Convert to using %pOFn instead of device_node.name
  mfd: madera: Don't use regmap_read_poll_timeout to poll for BOOT_DONE
  ...

Merge remote-tracking branch 'spi/topic/of' into spi-next

2018-10-21T16:00:17+00:00

Merge branch 'spi-4.20' into spi-next

2018-10-21T16:00:14+00:00

Merge branch 'spi-4.19' into spi-linus

2018-10-21T16:00:10+00:00

spi: Allow building SPI_BCM63XX_HSSPI on ARM-based SoCs

2018-10-21T11:08:27+00:00

ARM-based 63xx DSL platforms have the spi-bcm63xx-hsspi controller
present, allow using this driver there as well.

Signed-off-by: Florian Fainelli 
Signed-off-by: Mark Brown

spi: omap2-mcspi: Add slave mode support

2018-10-19T12:32:59+00:00

Add support to use McSPI controller as SPI slave. In slave mode, DMA TX
completion does not mean entire data has been shifted out as data might
still be stuck in FIFO waiting for master to clock the bus. Therefore,
add an IRQ handler for slave mode to know when entire data in FIFO has
been shifted out.

Signed-off-by: Vignesh R 
Signed-off-by: Mark Brown

spi: omap2-mcspi: Set FIFO DMA trigger level to word length

2018-10-19T12:32:58+00:00

McSPI has 32 byte FIFO in Transmit-Receive mode. Current code tries to
configuration FIFO watermark level for DMA trigger to be GCD of transfer
length and max FIFO size which would mean trigger level may be set to 32
for transmit-receive mode if length is aligned. This does not work in
case of SPI slave mode where FIFO always needs to have data ready
whenever master starts the clock. With DMA trigger size of 32 there will
be a small window during slave TX where DMA is still putting data into
FIFO but master would have started clock for next byte, resulting in
shifting out of stale data. Similarly, on Slave RX side there may be RX
FIFO overflow
Fix this by setting FIFO watermark for DMA trigger to word
length. This means DMA is triggered as soon as FIFO has space for word
length bytes and DMA would make sure FIFO is almost always full
therefore improving FIFO occupancy in both master and slave mode.

Signed-off-by: Vignesh R 
Signed-off-by: Mark Brown

spi: omap2-mcspi: Switch to readl_poll_timeout()

2018-10-19T12:32:57+00:00

Use standard readl_poll_timeout() macro for polling on status bits.

Signed-off-by: Vignesh R 
Signed-off-by: Mark Brown

spi: spi-mem: add stm32 qspi controller

2018-10-19T12:32:56+00:00

The qspi controller is a specialized communication interface
targeting single, dual or quad SPI Flash memories (NOR/NAND).

It can operate in any of the following modes:
-indirect mode: all the operations are performed using the quadspi
 registers
-read memory-mapped mode: the external Flash memory is mapped to the
 microcontroller address space and is seen by the system as if it was
 an internal memory

tested on:
-NOR: mx66l51235l
-NAND: MT29F2G01ABAGD

Signed-off-by: Ludovic Barre 
Signed-off-by: Mark Brown

spi: pic32-sqi: don't pass GFP_DMA32 to dma_alloc_coherent

2018-10-17T10:11:32+00:00

The DMA API does its own zone decisions based on the coherent_dma_mask.

Signed-off-by: Christoph Hellwig 
Signed-off-by: Mark Brown