linux.git/drivers/spi/Makefile, branch v6.16 Linux kernel source tree spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller 2025-04-06T22:26:10+00:00 Raju Rangoju Raju.Rangoju@amd.com 2025-04-02T12:15:14+00:00 b644c2776652671256edcd7a8e71161e212b59ac Register a new driver(spi_amd_pci) for the HID2 SPI controller using the PCI ID of the LPC bridge device. Add a new common probe function in spi_amd driver to encapsulate the code required for registering the controller driver. This function will be utilized by both the existing ACPI driver and the newly introduced PCI-based driver for the HID2 SPI controller. The MMIO register base address of the HID2 SPI controller can be obtained from the PCI LPC bridge registers. By implementing these changes, the DMA buffer will be correctly associated with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when the LPC bridge attempts DMA operations on addresses owned by the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Register a new driver(spi_amd_pci) for the HID2 SPI controller using the
PCI ID of the LPC bridge device.

Add a new common probe function in spi_amd driver to encapsulate the
code required for registering the controller driver. This function will be
utilized by both the existing ACPI driver and the newly introduced
PCI-based driver for the HID2 SPI controller. The MMIO register base
address of the HID2 SPI controller can be obtained from the PCI LPC bridge
registers.

By implementing these changes, the DMA buffer will be correctly associated
with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when
the LPC bridge attempts DMA operations on addresses owned by the HID2
SPI controller.

Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: sophgo: add SG2044 SPI NOR controller driver 2025-03-11T13:11:24+00:00 Longbin Li looong.bin@gmail.com 2025-03-04T08:35:43+00:00 de16c322eefbe9026d4eabc8ae934bb778cffd1d Add support for SG2044 SPI NOR controller in Sophgo SoC. Signed-off-by: Longbin Li <looong.bin@gmail.com> Link: https://patch.msgid.link/20250304083548.10101-3-looong.bin@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add support for SG2044 SPI NOR controller in Sophgo SoC.

Signed-off-by: Longbin Li <looong.bin@gmail.com>
Link: https://patch.msgid.link/20250304083548.10101-3-looong.bin@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add STM32MP25 SPI NOR support 2025-03-04T12:34:18+00:00 Mark Brown broonie@kernel.org 2025-03-04T12:34:18+00:00 5fac6c2785f95ddd73db33289dcd3cd5a68be226 Merge series from patrice.chotard@foss.st.com: This series adds SPI NOR support for STM32MP25 SoCs from STMicroelectronics. On STM32MP25 SoCs family, an Octo Memory Manager block manages the muxing, the memory area split, the chip select override and the time constraint between its 2 Octo SPI children. Due to these depedencies, this series adds support for: - Octo Memory Manager driver (not applied for SPI). - Octo SPI driver. - yaml schema for Octo Memory Manager and Octo SPI drivers. The device tree files adds Octo Memory Manager and its 2 associated Octo SPI chidren in stm32mp251.dtsi and adds SPI NOR support in stm32mp257f-ev1 board. 
Merge series from patrice.chotard@foss.st.com:

This series adds SPI NOR support for STM32MP25 SoCs from STMicroelectronics.

On STM32MP25 SoCs family, an Octo Memory Manager block manages the muxing,
the memory area split, the chip select override and the time constraint
between its 2 Octo SPI children.

Due to these depedencies, this series adds support for:
  - Octo Memory Manager driver (not applied for SPI).
  - Octo SPI driver.
  - yaml schema for Octo Memory Manager and Octo SPI drivers.

The device tree files adds Octo Memory Manager and its 2 associated Octo
SPI chidren in stm32mp251.dtsi and adds SPI NOR support in stm32mp257f-ev1
board.
spi: spi-qpic: add driver for QCOM SPI NAND flash Interface 2025-03-03T13:00:21+00:00 Md Sadre Alam quic_mdalam@quicinc.com 2025-02-24T11:14:14+00:00 7304d1909080ef0c9da703500a97f46c98393fcd This driver implements support for the SPI-NAND mode of QCOM NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20250224111414.2809669-3-quic_mdalam@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org> 
This driver implements support for the SPI-NAND mode of QCOM NAND Flash
Interface as a SPI-MEM controller with pipelined ECC capability.

Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Link: https://patch.msgid.link/20250224111414.2809669-3-quic_mdalam@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: stm32: Add OSPI driver 2025-03-03T13:00:14+00:00 Patrice Chotard patrice.chotard@foss.st.com 2025-02-19T08:00:53+00:00 79b8a705e26c08f8f09dd55f1dd56f2375973d2d Add STM32 OSPI driver, it supports : - support sNOR / sNAND devices. - Three functional modes: indirect, automatic-status polling, memory-mapped. - Single-, dual-, quad-, and octal-SPI communication. - Dual-quad communication. - Single data rate (SDR). - DMA channel for indirect mode. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://patch.msgid.link/20250219080059.367045-3-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add STM32 OSPI driver, it supports :
  - support sNOR / sNAND devices.
  - Three functional modes: indirect, automatic-status polling,
    memory-mapped.
  - Single-, dual-, quad-, and octal-SPI communication.
  - Dual-quad communication.
  - Single data rate (SDR).
  - DMA channel for indirect mode.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://patch.msgid.link/20250219080059.367045-3-patrice.chotard@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: offload-trigger: add PWM trigger driver 2025-02-07T20:17:10+00:00 David Lechner dlechner@baylibre.com 2025-02-07T20:09:01+00:00 ebb398ae1e052c4245b7bcea679fe073111db2ce Add a new driver for a generic PWM trigger for SPI offloads. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-4-e48a489be48c@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add a new driver for a generic PWM trigger for SPI offloads.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-4-e48a489be48c@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: add basic support for SPI offloading 2025-02-07T20:17:07+00:00 David Lechner dlechner@baylibre.com 2025-02-07T20:08:58+00:00 8e02d188698851436f76038ea998b726193d1b10 Add the basic infrastructure to support SPI offload providers and consumers. SPI offloading is a feature that allows the SPI controller to perform transfers without any CPU intervention. This is useful, e.g. for high-speed data acquisition. SPI controllers with offload support need to implement the get_offload and put_offload callbacks and can use the devm_spi_offload_alloc() to allocate offload instances. SPI peripheral drivers will call devm_spi_offload_get() to get a reference to the matching offload instance. This offload instance can then be attached to a SPI message to request offloading that message. It is expected that SPI controllers with offload support will check for the offload instance in the SPI message in the ctlr->optimize_message() callback and handle it accordingly. CONFIG_SPI_OFFLOAD is intended to be a select-only option. Both consumer and provider drivers should `select SPI_OFFLOAD` in their Kconfig to ensure that the SPI core is built with offload support. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-1-e48a489be48c@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add the basic infrastructure to support SPI offload providers and
consumers.

SPI offloading is a feature that allows the SPI controller to perform
transfers without any CPU intervention. This is useful, e.g. for
high-speed data acquisition.

SPI controllers with offload support need to implement the get_offload
and put_offload callbacks and can use the devm_spi_offload_alloc() to
allocate offload instances.

SPI peripheral drivers will call devm_spi_offload_get() to get a
reference to the matching offload instance. This offload instance can
then be attached to a SPI message to request offloading that message.

It is expected that SPI controllers with offload support will check for
the offload instance in the SPI message in the ctlr->optimize_message()
callback and handle it accordingly.

CONFIG_SPI_OFFLOAD is intended to be a select-only option. Both
consumer and provider drivers should `select SPI_OFFLOAD` in their
Kconfig to ensure that the SPI core is built with offload support.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-1-e48a489be48c@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: spi-kspi2: Add KEBA SPI controller support 2024-12-04T16:25:22+00:00 Gerhard Engleder eg@keba.com 2024-12-02T19:40:03+00:00 1a90aae3b25b72e639da6062e0dc5efb9cff58f1 The KEBA SPI controller is found in the system FPGA of KEBA PLC devices. It is used to connect the SPI flash chip of the FPGA and some SPI devices. It is a simple SPI controller with configurable speed. The hardware supports only single byte transfers. There are no FIFOs or interrupts. Signed-off-by: Gerhard Engleder <eg@keba.com> Link: https://patch.msgid.link/20241202194003.57679-1-gerhard@engleder-embedded.com Signed-off-by: Mark Brown <broonie@kernel.org> 
The KEBA SPI controller is found in the system FPGA of KEBA PLC devices.
It is used to connect the SPI flash chip of the FPGA and some SPI
devices.

It is a simple SPI controller with configurable speed. The hardware
supports only single byte transfers. There are no FIFOs or interrupts.

Signed-off-by: Gerhard Engleder <eg@keba.com>
Link: https://patch.msgid.link/20241202194003.57679-1-gerhard@engleder-embedded.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: apple: Add driver for Apple SPI controller 2024-11-06T14:15:39+00:00 Hector Martin marcan@marcan.st 2024-11-06T07:54:01+00:00 c36212b2610d09eb42142beb0d5613c70206c658 This SPI controller is present in Apple SoCs such as the M1 (t8103) and M1 Pro/Max (t600x). It is a relatively straightforward design with two 16-entry FIFOs, arbitrary transfer sizes (up to 2**32 - 1) and fully configurable word size up to 32 bits. It supports one hardware CS line which can also be driven via the pinctrl/GPIO driver instead, if desired. TX and RX can be independently enabled. There are a surprising number of knobs for tweaking details of the transfer, most of which we do not use right now. Hardware CS control is available, but we haven't found a way to make it stay low across multiple logical transfers, so we just use software CS control for now. There is also a shared DMA offload coprocessor that can be used to handle larger transfers without requiring an IRQ every 8-16 words, but that feature depends on a bunch of scaffolding that isn't ready to be upstreamed yet, so leave it for later. The hardware shares some register bit definitions with spi-s3c24xx which suggests it has a shared legacy with Samsung SoCs, but it is too different to warrant sharing a driver. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Janne Grunau <j@jannau.net> Link: https://patch.msgid.link/20241106-asahi-spi-v5-2-e81a4f3a8e19@jannau.net Signed-off-by: Mark Brown <broonie@kernel.org> 
This SPI controller is present in Apple SoCs such as the M1 (t8103) and
M1 Pro/Max (t600x). It is a relatively straightforward design with two
16-entry FIFOs, arbitrary transfer sizes (up to 2**32 - 1) and fully
configurable word size up to 32 bits. It supports one hardware CS line
which can also be driven via the pinctrl/GPIO driver instead, if
desired. TX and RX can be independently enabled.

There are a surprising number of knobs for tweaking details of the
transfer, most of which we do not use right now. Hardware CS control
is available, but we haven't found a way to make it stay low across
multiple logical transfers, so we just use software CS control for now.

There is also a shared DMA offload coprocessor that can be used to handle
larger transfers without requiring an IRQ every 8-16 words, but that
feature depends on a bunch of scaffolding that isn't ready to be
upstreamed yet, so leave it for later.

The hardware shares some register bit definitions with spi-s3c24xx which
suggests it has a shared legacy with Samsung SoCs, but it is too
different to warrant sharing a driver.

Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Janne Grunau <j@jannau.net>
Link: https://patch.msgid.link/20241106-asahi-spi-v5-2-e81a4f3a8e19@jannau.net
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: spi-mem: Add Realtek SPI-NAND controller 2024-10-21T11:49:38+00:00 Chris Packham chris.packham@alliedtelesis.co.nz 2024-10-15T22:54:34+00:00 42d20a6a61b8fccbb57d80df1ccde7dd82d5bbd6 Add a driver for the SPI-NAND controller on the RTL9300 family of devices. The controller supports * Serial/Dual/Quad data with * PIO and DMA data read/write operation * Configurable flash access timing There is a separate ECC controller on the RTL9300 which isn't currently supported (instead we rely on the on-die ECC supported by most SPI-NAND chips). Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://patch.msgid.link/20241015225434.3970360-4-chris.packham@alliedtelesis.co.nz Signed-off-by: Mark Brown <broonie@kernel.org> 
Add a driver for the SPI-NAND controller on the RTL9300 family of
devices.

The controller supports
* Serial/Dual/Quad data with
* PIO and DMA data read/write operation
* Configurable flash access timing

There is a separate ECC controller on the RTL9300 which isn't currently
supported (instead we rely on the on-die ECC supported by most SPI-NAND
chips).

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Link: https://patch.msgid.link/20241015225434.3970360-4-chris.packham@alliedtelesis.co.nz
Signed-off-by: Mark Brown <broonie@kernel.org>