linux.git/drivers/spi/Makefile, branch master Linux kernel source tree spi: Add KUnit coverage for DMA mapping error paths 2026-08-14T15:48:52+00:00 Honghui Jiang jiang_hh2019@163.com 2026-08-14T03:14:18+00:00 9b81a87c5244bc139357460a262d4536226ba41d Add KUnit tests for the __spi_map_msg() error paths. The tests verify that a later TX or RX mapping failure clears the mapping state of earlier transfers and leaves cur_{tx,rx}_dma_dev identifying the current mapping device. A zero-length transfer causes sg_alloc_table() to return -EINVAL, providing deterministic failure injection without test hooks. Additional cases cover successful map/unmap and a message which requires no mapping. Build the DMA suite as a separate translation unit, exposing the two internal mapping helpers only for KUnit through the local internal header. Enable SPI in the default and all-tests KUnit configurations so the suite is exercised there. Signed-off-by: Honghui Jiang <jiang_hh2019@163.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260814031419.43378-5-jiang_hh2019@163.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add KUnit tests for the __spi_map_msg() error paths. The tests verify
that a later TX or RX mapping failure clears the mapping state of
earlier transfers and leaves cur_{tx,rx}_dma_dev identifying the
current mapping device.

A zero-length transfer causes sg_alloc_table() to return -EINVAL,
providing deterministic failure injection without test hooks.
Additional cases cover successful map/unmap and a message which
requires no mapping.

Build the DMA suite as a separate translation unit, exposing the two
internal mapping helpers only for KUnit through the local internal
header. Enable SPI in the default and all-tests KUnit configurations so
the suite is exercised there.

Signed-off-by: Honghui Jiang <jiang_hh2019@163.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20260814031419.43378-5-jiang_hh2019@163.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: ma35d1-qspi: Add Nuvoton MA35D1 QSPI controller support 2026-07-31T20:29:22+00:00 Chi-Wen Weng cwweng@nuvoton.com 2026-07-31T02:38:18+00:00 78b16af159ae6d1f5506697c1f08d8172afdc037 Add SPI controller driver support for the Quad SPI controller found in Nuvoton MA35D1 SoCs. The controller provides two native chip selects and supports standard SPI and spi-mem operations, including single-bit full-duplex transfers and dual or quad half-duplex transfers. Implement 8-bit PIO transfers, per-operation clock configuration, clock and reset handling, and direct execution of SPI memory operations. Limit individual transfers to 4 KiB and SPI messages to 8 KiB to keep the PIO polling path bounded. Read the optional num-cs property and fall back to the hardware default of two chip selects when it is not present. Active-high chip select and DMA transfers are not supported by this initial implementation. Signed-off-by: Chi-Wen Weng <cwweng@nuvoton.com> Link: https://patch.msgid.link/20260731023818.1626075-3-cwweng.linux@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add SPI controller driver support for the Quad SPI controller found in
Nuvoton MA35D1 SoCs.

The controller provides two native chip selects and supports standard SPI
and spi-mem operations, including single-bit full-duplex transfers and
dual or quad half-duplex transfers. Implement 8-bit PIO transfers,
per-operation clock configuration, clock and reset handling, and direct
execution of SPI memory operations.

Limit individual transfers to 4 KiB and SPI messages to 8 KiB to keep the
PIO polling path bounded. Read the optional num-cs property and fall back
to the hardware default of two chip selects when it is not present.

Active-high chip select and DMA transfers are not supported by this
initial implementation.

Signed-off-by: Chi-Wen Weng <cwweng@nuvoton.com>
Link: https://patch.msgid.link/20260731023818.1626075-3-cwweng.linux@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: spacemit: introduce SpacemiT K1 SPI controller driver 2026-05-04T13:21:00+00:00 Alex Elder elder@riscstar.com 2026-05-03T01:30:52+00:00 efcd8b9d111177d48c841d09beca43b15d5b9e5f This patch introduces the driver for the SPI controller found in the SpacemiT K1 SoC. Currently the driver supports master mode only. The SPI hardware implements RX and TX FIFOs, 32 entries each, and supports both PIO and DMA mode transfers. Signed-off-by: Alex Elder <elder@riscstar.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://patch.msgid.link/20260502-spi-spacemit-k1-v10-2-f412e1ae8a34@riscstar.com Signed-off-by: Mark Brown <broonie@kernel.org> 
This patch introduces the driver for the SPI controller found in the
SpacemiT K1 SoC.  Currently the driver supports master mode only.
The SPI hardware implements RX and TX FIFOs, 32 entries each, and
supports both PIO and DMA mode transfers.

Signed-off-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://patch.msgid.link/20260502-spi-spacemit-k1-v10-2-f412e1ae8a34@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: dw: Remove not-going-to-be-supported code for Baikal SoC 2026-01-29T11:54:47+00:00 Andy Shevchenko andriy.shevchenko@linux.intel.com 2026-01-27T21:05:41+00:00 da0a672268b34279aa999664860e6becc38f3f51 As noticed in the discussion [1] the Baikal SoC and platforms are not going to be finalized, hence remove stale code. Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260127210541.4068379-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org> 
As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.

Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20260127210541.4068379-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Axiado AX3000 SoC SPI DB controller driver 2026-01-13T14:02:17+00:00 Mark Brown broonie@kernel.org 2026-01-13T14:02:17+00:00 26cbb4dd58ae1ca83319e73e9397b06a8ca961c6 Merge series from Vladimir Moravcevic <vmoravcevic@axiado.com>: This series introduces new SPI controller driver for Axiado AX3000 SoC and its evaluation board. The SPI controller provides: - Full-duplex and half-duplex transfer support - Configurable clock polarity and phase - Interrupt-driven Functionality has been verified using the `jedec,spi-nor` interface to access onboard flash memory. This ensures compatibility with common NOR flash devices used in boot and storage subsystem. Further improvements, including performance tuning and extended hardware feature support, will be submitted in follow-up patches. 
Merge series from Vladimir Moravcevic <vmoravcevic@axiado.com>:

This series introduces new SPI controller driver for Axiado AX3000 SoC
and its evaluation board.

The SPI controller provides:
- Full-duplex and half-duplex transfer support
- Configurable clock polarity and phase
- Interrupt-driven

Functionality has been verified using the `jedec,spi-nor` interface to
access onboard flash memory. This ensures compatibility with common NOR
flash devices used in boot and storage subsystem.

Further improvements, including performance tuning and extended hardware
feature support, will be submitted in follow-up patches.
spi: axiado: Add driver for Axiado SPI DB controller 2026-01-09T13:21:55+00:00 Vladimir Moravcevic vmoravcevic@axiado.com 2026-01-08T07:44:38+00:00 e75a6b00ad7962a7ed1c9c777e9ab1eb29043ec8 The Axiado SPI controller is present in AX3000 SoC and Evaluation Board. This controller is operating in Host only mode. Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com> Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com> Signed-off-by: Vladimir Moravcevic <vmoravcevic@axiado.com> Link: https://patch.msgid.link/20260107-axiado-ax3000-soc-spi-db-controller-driver-v3-2-726e70cf19ad@axiado.com Signed-off-by: Mark Brown <broonie@kernel.org> 
The Axiado SPI controller is present in AX3000 SoC and Evaluation Board.
This controller is operating in Host only mode.

Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com>
Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com>
Signed-off-by: Vladimir Moravcevic <vmoravcevic@axiado.com>
Link: https://patch.msgid.link/20260107-axiado-ax3000-soc-spi-db-controller-driver-v3-2-726e70cf19ad@axiado.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: atcspi200: Add support for Andes ATCSPI200 SPI 2025-12-18T09:53:54+00:00 Mark Brown broonie@kernel.org 2025-12-18T09:53:54+00:00 65ccce35fa7a3b52713bd128fd211a80afc08abd Merge series from CL Wang <cl634@andestech.com>: This series adds support for the Andes ATCSPI200 SPI controller. 
Merge series from CL Wang <cl634@andestech.com>:

This series adds support for the Andes ATCSPI200 SPI controller.
spi: atcspi200: Add ATCSPI200 SPI controller driver 2025-12-17T12:04:53+00:00 CL Wang cl634@andestech.com 2025-12-15T13:23:48+00:00 34e3815ea4597131d4324a4aa243d2201e672005 Add driver for the Andes ATCSPI200 SPI controller. Signed-off-by: CL Wang <cl634@andestech.com> Link: https://patch.msgid.link/20251215132349.513843-3-cl634@andestech.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add driver for the Andes ATCSPI200 SPI controller.

Signed-off-by: CL Wang <cl634@andestech.com>
Link: https://patch.msgid.link/20251215132349.513843-3-cl634@andestech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: add driver for NXP XSPI controller 2025-12-17T12:04:47+00:00 Haibo Chen haibo.chen@nxp.com 2025-12-16T03:20:14+00:00 29c8c00d9f9db5fb659b6f05f9e8964afc13f3e2 Add driver support for NXP XSPI controller. XSPI is a flexible SPI host controller which supports up to 2 external devices (2 CS). It support Single/Dual/Quad/Octal mode data transfer. The difference between XSPI and Flexspi: 1.the register layout is total different. 2.XSPI support multiple independent execution environments (EENVs) for HW virtualization with some limitations. Each EENV has its own interrupt and its own set of programming registers that exists in a specific offset range in the XSPI memory map. The main environment (EENV0) address space contains all of the registers for controlling EENV0 plus all of the general XSPI control and programming registers. The register mnemonics for the user environments (EENV1 to EENV4) have "_SUB_n" appended to the mnemonic for the corresponding main-environment register. Current driver based on EENV0, which means system already give EENV0 right to linux. This driver use SPI memory interface of the SPI framework to issue flash memory operations. Tested this driver with UBIFS and mtd_debug on NXP i.MX943 EVK board which has one spi nor MT35XU512ABA flash. Now this driver has the following key features: - Support up to OCT DDR mode - Support AHB read - Support IP read and IP write - Support two CS Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20251216-xspi-v7-2-282525220979@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add driver support for NXP XSPI controller.

XSPI is a flexible SPI host controller which supports up to
2 external devices (2 CS). It support Single/Dual/Quad/Octal
mode data transfer.

The difference between XSPI and Flexspi:
1.the register layout is total different.
2.XSPI support multiple independent execution environments
(EENVs) for HW virtualization with some limitations. Each EENV
has its own interrupt and its own set of programming registers
that exists in a specific offset range in the XSPI memory map.
The main environment (EENV0) address space contains all of the
registers for controlling EENV0 plus all of the general XSPI
control and programming registers. The register mnemonics for
the user environments (EENV1 to EENV4) have "_SUB_n" appended
to the mnemonic for the corresponding main-environment register.

Current driver based on EENV0, which means system already give
EENV0 right to linux.

This driver use SPI memory interface of the SPI framework to
issue flash memory operations. Tested this driver with UBIFS
and mtd_debug on NXP i.MX943 EVK board which has one spi nor
MT35XU512ABA flash. Now this driver has the following key
features:
- Support up to OCT DDR mode
- Support AHB read
- Support IP read and IP write
- Support two CS

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20251216-xspi-v7-2-282525220979@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: add support for microchip "soft" spi controller 2025-11-14T13:54:43+00:00 Prajna Rajendra Kumar prajna.rajendrakumar@microchip.com 2025-11-14T10:45:45+00:00 059f545832be85d29ac9ccc416a16f647aa78485 Introduce driver support for the Microchip FPGA CoreSPI IP. This driver supports only Motorola SPI mode and frame size of 8-bits. TI/NSC modes and wider frame sizes are not currently supported. Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251114104545.284765-4-prajna.rajendrakumar@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Introduce driver support for the Microchip FPGA CoreSPI IP.

This driver supports only Motorola SPI mode and frame size of 8-bits.
TI/NSC modes and wider frame sizes are not currently supported.

Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251114104545.284765-4-prajna.rajendrakumar@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>